SoC Targeting Workflows
R2026bSoC Blockset™ for AMD offers two workflows for generating bitstreams, software, and deploying your model on an SoC device.
IP core generation workflow: Use a provided architecture (fixed or auto-generated reference design), and use Simulink® to design your IP core.
SoC modeling and generation workflow: Use Simulink to design an architecture and an IP core from scratch.
IP Core Generation Workflow
In this workflow, SoC Blockset for AMD provides the system architecture as a reference design. You can then design your IP core with Simulink. The IP core generation workflow takes you through the steps to integrate your IP in the reference design, generate HDL code, and deploy it on hardware.
To get started with this workflow, see Targeting FPGA and SoC Hardware Overview and Hardware-Software Co-Design Workflow for SoC Platforms. For an example using this workflow, see Get Started with IP Core Generation from Simulink Model (HDL Coder).
SoC Modeling and Generation Workflow
In this workflow, you design the whole system, including architecture and IP cores with Simulink and SoC Blockset for AMD library blocks. Then, use the SoC Builder tool to guide you through the steps required to build hardware and software executables, load them on an SoC device, and execute.
To get started with this workflow, see Use Template to Create SoC Model and Create an SoC Project Application. For an example of using the SoC Builder tool, see Streaming Data from Hardware to Software Using AMD SoC Devices.
Choose Workflow
This section helps you decide when to choose the IP core generation workflow or the SoC modeling and generation workflow.
IP Core Generation
Best when you want to integrate your FPGA algorithm into a reference design with predefined interfaces
Suitable for rapid prototyping and when your interface requirements match the available reference designs
SoC Modeling and Generation
Recommended when you need custom interfaces or greater control over hardware-software partitioning
Useful for advanced designs that require managing multiple custom interfaces or integrating with a larger SoC system
Provides full flexibility to modify and extend the reference design per your requirements
Export Reference Design
Use Simulink to export your architecture as a custom reference design, leaving a placeholder for IP generation downstream.
In this workflow, you design the system architecture with Simulink and SoC
Blockset for AMD library blocks, leaving a place holder for the IP core. Use the socExportReferenceDesign function to generate a custom reference design
from the system architecture. Once generated, use this reference design with the IP core
generation workflow to integrate different IP cores, and for algorithm
development.
Transition to IP Core Generation Workflow
You can use the socExportReferenceDesign function to transition from the SoC modeling
and generation workflow to the IP core generation workflow.
Use this function to export a reference design from an SoC Blockset for AMD model. Then, integrate your IP core to the reference design and deploy it to an SoC device using the HDL Workflow Advisor tool.
For an example of using the socExportReferenceDesign function,
see Export Custom Reference Design.
These workflows require both SoC Blockset for AMD and HDL Coder™ products.
