IP core clock frequency (MHz)

Clock for all Simulink-based generated HDL IP cores

Model Configuration Pane: Target hardware resources / FPGA design (top-level)

Description

The . A single clock drives all IP and is used for both datapath and configuration register logic.

Settings

100 (default)

Default: 100

Programmatic Use

Parameter:

Type:

Values: 100

Default: 100

Version History

Introduced in R2019a