FPGA IP Block Generator

R2026b

Generate Simulink block for FPGA IP core

Since R2023a

Description

Use the FPGA IP Block Generator tool to generate a Simulink^® block for an existing FPGA IP core. The tool takes you through the steps to generate a library block that you can integrate into your SoC Simulink model. You can then simulate the model and use the SoC Builder tool to build and deploy the model on a hardware board.

Using this tool, you can:

• Import an AMD^® or custom FPGA IP as a Simulink block.

• Generate the editable simulation and customization files with the .m and .tcl extensions, respectively.

• Specify the block name, library name, and library location.

• Include multiple instances of the generated block in the same Simulink model.

• Specify constraints on the FPGA IP core.

• Review or update the FPGA IP interfaces that the tool adds as ports to the generated block.

• Review clock and reset interfaces and select the required source for these interfaces.

• Specify a device tree file for the FPGA IP and the pre- and post-load scripts.

You can also import multiple FPGA IP cores into the Simulink model as a single block. To import multiple FPGA IP cores, package multiple IPs into single IP in Vivado^®, and then use the FPGA IP Block Generator tool.

The tool supports the AXI4-Stream, AXI4-Stream Video, AXI4 Master, I/O, AXI4-Lite, and AXI4 Slave FPGA IP interfaces for the block generation. You can add these interfaces as ports to the generated block.

Open the FPGA IP Block Generator

• Simulink Toolstrip: On the System on Chip tab, click FPGA IP Block Generator.

• MATLAB^® command prompt: Enter fpgaIPBlockGenerator.

Examples

• Import FPGA IP Core into SoC Model
• Import Custom FPGA IP into SoC Blockset Design
• Monitor and Analyze Applications Targeted to AMD RFSoC Devices

Version History

Introduced in R2023a

R2026b: HDL IP Importer renamed to FPGA IP Block Generator

The HDL IP Importer tool has been renamed to FPGA IP Block Generator.

To open the FPGA IP Block Generator tool, enter the fpgaIPBlockGenerator command at the MATLAB command prompt. Using the hdlIPImporter command, which previously opened the HDL IP Importer tool, is not recommended and will be removed in a future release. If you use the hdlIPImporter command in the MATLAB command prompt, the command now opens the FPGA IP Block Generator tool.