FPGA design (mem channels)
Interconnect clock frequency (MHz)
Frequency of the master datapath to the interconnect controller in MHz.
Interconnect data width (bits)
Data width of master datapath to interconnect controller in bits.
Interconnect FIFO depth (num bursts)
Specify depth of data FIFO, in units of bursts. When the writer has no buffers to write to, the FIFO can absorb data until a buffer becomes available. This value is the maximum number of bursts that can be buffered before data gets dropped.
Interconnect almost-full depth
Specify a number that asserts a backpressure signal from the channel to the data source. To avoid dropping data, set a high watermark, allowing the data producer enough time to react to backpressure. This number must be smaller than the FIFO depth.