To comply with composite signal requirements and limitations, Simulink® may add hidden Bus to Vector and Signal Conversion blocks to your model. These additions help you avoid manually converting or refactoring your models, which can be time consuming and error prone.
When a block requires a vector but receives a virtual bus, a hidden Bus to Vector block may convert the bus to a vector. Bus to Vector blocks are virtual and do not affect simulation results, code generation, or performance. However, when a bus is treated as a vector, the elements of the bus become inaccessible.
To receive warnings or errors when a bus is treated as a vector, set the
Bus signal treated as vector configuration parameter to
respectively. These settings allow you to identify potential problems at the source,
instead of at downstream blocks that expect a bus.
To correct buses used as vectors:
In the Model Advisor for the top model, run the Check bus signals treated as vectors check and perform the recommended actions.
Replace the related Bus Creator block with a Mux block, which creates a vector.
When updating a diagram before simulation or code generation, Simulink might automatically convert a virtual bus to a nonvirtual bus or a nonvirtual bus to a virtual bus. For example, Simulink implicitly converts a bus when:
A block, such as an S-Function block or a Stateflow® chart, receives a virtual bus, but requires a nonvirtual bus.
A referenced model receives a nonvirtual bus, but the corresponding input port specifies a virtual bus.
A root-level output port receives a nonvirtual bus, but specifies a virtual bus.
Simulink inserts hidden Signal Conversion blocks into the model
where needed. If a
Simulink.Bus object is not specified for a
virtual bus, the conversion to a nonvirtual bus fails and you receive an
Unlike Bus to Vector blocks, Signal Conversion blocks do not affect the structure of the output bus.