Dead Zone Dynamic

Provide dynamic region of zero output

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Libraries:
Simulink / Discontinuities
HDL Coder / Discontinuities

Description

The Dead Zone Dynamic block generates a region of zero output based on dynamic input signals that specify the upper and lower limit. The block output depends on the input u, and the values of the input signals up and lo.

Input	Output
u >= lo and u <= up	Zero
u > up	u – up
u < lo	u – lo

The Dead Zone Dynamic block is a masked subsystem and does not have any parameters.

Ports

Input

u — Input signal

scalar | vector

Input signal to the dead zone algorithm.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

lo — Lower limit for the dead zone

scalar | vector

Dynamic value providing the lower bound of the region of zero output. When the input is less than lo then the output value is shifted down by value of lo.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

up — Upper limit for the dead zone

scalar

Dynamic value providing the upper bound of the region of zero output. When the input is greater than up then the output value is shifted down by value of up.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Output

y — Output signal

scalar | vector

Output signal after the dynamic dead zone algorithm is applied to the input signal.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Block Characteristics

Data Types	double | fixed point | integer | single
Direct Feedthrough	yes
Multidimensional Signals	no
Variable-Size Signals	no
Zero-Crossing Detection	no

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).
SynthesisAttributes	Specifies the synthesis attributes for the blocks and block output signals in the model. The generated HDL code contains these attributes. For more information, see SynthesisAttributes (HDL Coder).

Native Floating Point
LatencyStrategy	Specify whether to map the blocks in your design to inherit, Max, Min, Zero, or Custom for the floating-point operator. The default is inherit. See also LatencyStrategy (HDL Coder).
NFPCustomLatency	To specify a value, set LatencyStrategy to Custom. HDL Coder adds latency equal to the value that you specify for the NFPCustomLatency setting. See also NFPCustomLatency (HDL Coder).

Latency Details

This block has multi-cycle implementations that introduce additional latency in the generated code. To see the added latency, view the generated model or validation model. See Generated Model and Validation Model (HDL Coder).

Native Floating-Point Latency

Floating-Point Type	LatencyStrategy Property Setting	Latency (In Cycles)	Custom Latency Support
Double	Min	6	Yes
	Max	11
Single	Min	6
	Max	11

Data Type Support

The block supports these data types for HDL code generation:

Input Port	Dimension	Fixed-Point	Floating-Point	Built-in Integers	Bus	Boolean	Complex Signal
Port_1	Scalar Vector Matrix ( 2-D and 3-D)	Yes	Single Double	Yes	Yes	Yes	Yes

Optimizations

You can use these HDL Coder optimizations to optimize the speed, area, and I/Os.

Area Optimization

Optimization	Description
Resource Sharing (HDL Coder)	Resource sharing is an area optimization in which HDL Coder identifies multiple functionally equivalent resources and replaces them with a single resource.
Streaming (HDL Coder)	Streaming is an area optimization in which HDL Coder transforms a vector data path to a scalar data path (or to several smaller-sized vector data paths).

Speed Optimization

Optimization	Description
Specify Distributed Pipelining Settings (HDL Coder)	Distributed pipelining, or register retiming, is a speed optimization that moves existing delays in a design to reduce the critical path while preserving functional behavior.
Clock-Rate Pipelining (HDL Coder)	Clock-rate pipelining is an optimization framework in HDL Coder that allows other speed and area optimizations to introduce latency at the clock rate.
Critical Path Estimation (HDL Coder)	To quickly identify the most likely critical path in your design, use Critical Path Estimation. Critical path estimation speeds up the iterative process of finding the critical path. To know blocks that are characterized in critical path estimation, see Characterized Blocks (HDL Coder).

I/O Optimization

Optimization	Description
Frame to Sample Conversion (HDL Coder)	To optimize the I/O needed for your design, use frame-to-sample conversion. This optimization converts frame-based vector or matrix inputs to smaller-sized samples or pixels for HDL code generation to target stream-based hardware and reduce the FPGA I/O needed to handle large input and output signals.

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a

R2026a: Native floating-point support

You can now generate HDL code in the native floating-point mode for the Dead Zone Dynamic block by using input data types of single or double. You can specify the latency strategy for the block by using the LatencyStrategy HDL block property.

R2026a: Specify synthesis attributes for blocks and block output signals

Use the SynthesisAttributes HDL block property to specify the synthesis attributes for the block and its output signals. HDL Coder includes these attributes in the generated HDL code.