Dead Zone

Provide region of zero output

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Libraries:
Simulink / Discontinuities
HDL Coder / Discontinuities

Description

The Dead Zone block generates zero output within a specified region, called its dead zone. You specify the lower limit (LL) and upper limit (UL) of the dead zone as the Start of dead zone and End of dead zone parameters. The block output depends on the input (U) and the values for the lower and upper limits.

Input	Output
U >= LL and U <= UL	Zero
U > UL	U – UL
U < LL	U – LL

Examples

View Dead Zone Output on Sine Wave

The effect of the Dead Zone block on a sine wave.

Open Model

Ports

Input

Port_1 — Input signal

scalar | vector

Input signal to the dead-zone algorithm.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Output

Port_1 — Output signal

scalar | vector

Output signal after the dead-zone algorithm is applied to the input signal.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

Parameters

Start of dead zone — Specify the lower bound of the dead zone

'-0.5' (default) | scalar | vector

Specify dead zone lower limit. Set the value for Start of dead zone less than or equal to End of dead zone. When the input value is less than Start of dead zone, then the block shifts the output value down by the Start of dead zone value.

Programmatic Use

Block Parameter: LowerValue

Type: character vector

Value: scalar or vector less than or equal to UpperValue.

Default: '-0.5'

End of dead zone — Specify the upper limit of the dead zone

'0.5' (default) | scalar | vector

Specify dead zone upper limit. Set the value for End of dead zone greater than or equal to Start of dead zone. When the input value is greater than End of dead zone, then the block shifts the output value down by the End of dead zone value.

Programmatic Use

Block Parameter: UpperValue

Type: character vector

Value: scalar or vector greater than or equal to LowerValue.

Default: '0.5'

Saturate on integer overflow — Choose the behavior when integer overflow occurs

off (default) | on

Action	Reasons for Taking This Action	What Happens for Overflows	Example
Select this check box.	Your model has possible overflow, and you want explicit saturation protection in the generated code.	Overflows saturate to either the minimum or maximum value that the data type can represent.	The maximum value that the int8 (signed, 8-bit integer) data type can represent is 127. Any block operation result greater than this maximum value causes overflow of the 8-bit integer. With the check box selected, the block output saturates at 127. Similarly, the block output saturates at a minimum output value of -128.
Do not select this check box.	You want to optimize efficiency of your generated code. You want to avoid overspecifying how a block handles out-of-range signals. For more information, see Troubleshoot Signal Range Errors.	Overflows wrap to the appropriate value that is representable by the data type.	The maximum value that the int8 (signed, 8-bit integer) data type can represent is 127. Any block operation result greater than this maximum value causes overflow of the 8-bit integer. With the check box cleared, the software interprets the overflow-causing value as int8, which can produce an unintended result. For example, a block result of 130 (binary 1000 0010) expressed as int8, is -126.

When you select this check box, saturation applies to every internal operation on the block, not just the output or result. Usually, the code generation process can detect when overflow is not possible. In this case, the code generator does not produce saturation code.

Programmatic Use

Block Parameter: DoSatur

Type: character vector

Value: 'off' | 'on'

Default: 'off'

Treat as gain when linearizing — Specify the gain value

On (default) | boolean

The linearization commands in Simulink^® software treat this block as a gain in state space. Select this check box to cause the commands to treat the gain as 1. Clear the box to have the commands treat the gain as 0.

Programmatic Use

Block Parameter: LinearizeAsGain

Type: character vector

Value: 'off' | 'on'

Default: 'on'

Enable zero-crossing detection — Enable zero-crossing detection

on (default) | off

Select to enable zero-crossing detection. For more information, see Zero-Crossing Detection.

Programmatic Use

Block Parameter: ZeroCross

Type: character vector | string

Values: 'off' | 'on'

Default: 'on'

Sample time (-1 for inherited) — Interval between samples

-1 (default) | scalar | vector

Specify the time interval between samples. To inherit the sample time, set this parameter to -1. For more information, see Specify Sample Time.

Dependencies

This parameter is visible only if you set it to a value other than -1. To learn more, see Blocks for Which Sample Time Is Not Recommended.

Programmatic Use

Block Parameter: SampleTime

Type: string scalar or character vector

Default: "-1"

Block Characteristics

Data Types	double | fixed point | integer | single
Direct Feedthrough	yes
Multidimensional Signals	no
Variable-Size Signals	no
Zero-Crossing Detection	yes

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a