Single Modulus Prescaler
Integer clock divider that divides frequency of input signal
Mixed-Signal Blockset / PLL / Building Blocks
The Single Modulus Prescaler subsystem block divides the frequency of the input signal by a tunable integer value, N, passed to the div-by port. In frequency synthesizer circuits, such as a phase-locked loop (PLL) system, these prescalers divide the VCO output frequency by an integer value. The resulting lower frequency at the prescaler output port is comparable to the reference input at the PFD block. The Single Modulus Prescaler is also termed as integer clock divider.
clk in — Input clock frequency
Input clock frequency, specified as a scalar. In a PLL system, the clk in port is connected to the output port of a VCO block.
div-by — Ratio of output to input clock frequency
Ratio of output to input clock frequency, expressed as a scalar integer.
Enable increased buffer size — Enable increased buffer size
off (default) | on
Select to enable increased buffer size during simulation. This increases the buffer size of the Logic Decision inside the Single Modulus Prescaler block. By default, this option is deselected.
Buffer size — Number of samples of the input buffering available during simulation
1 (default) | positive integer scalar
Number of samples of the input buffering available during simulation, specified as a positive integer scalar. This sets the buffer size of the Logic Decision inside the Single Modulus Prescaler block.
Selecting different simulation solver or sampling strategies can change the number of input samples needed to produce an accurate output sample. Set the Buffer size to a large enough value so that the input buffer contains all the input samples required.
This parameter is only available when Enable increased buffer size option is selected in the Block Parameters dialog box.
get_param(gcb,'NBuffer')to view the current value of Buffer size.
set_param(gcb,'NBuffer',value)to set Buffer size to a specific value.
Inside the Mask
The Single Modulus Prescaler block contains the integer clock divider subsystem. Inside the subsystem, a trigger port tracks the rising edges of the input clock signal received at clk in port. The output sends a pulse only after N cycles have been detected. As a result, the input clock frequency reduces by a factor of N.
 Razavi, Behzad. RF Microelectronics. Upper Saddle River, NJ: Prentice Hall PTR, 1998.
Introduced in R2019a