Main Content

Integer clock divider with two divider ratios

**Library:**Mixed-Signal Blockset / PLL / Building Blocks

The Dual Modulus Prescaler subsystem block consists of a program counter, a swallow counter and a prescaler.

When the block first receives an input signal, the pulse swallow function is
activated. The prescaler divides the input signal frequency by (*N*+1),
where *N* is defined by the **Prescaler divider value
(N)** parameter. Both the program and swallow counters start counting. The
swallow counter resets after counting to *S* pulses, or
(*N*+1)S cycles, where *S* is defined by the
**Swallow counter value (S)** parameter. Then, the pulse swallow
function is deactivated, and the prescaler divides the input frequency by
*N*.

Since the program counter has already sensed S pulses, it requires
(*P*-*S*) more pulses, or
(*P*-*S*)*N* cycles to reach
overflow, where *P* is defined by the **Program counter value
(P)** parameter. The cycle repeats after both counters are reset.

The effective divider value of the dual modulus prescaler is the ratio of the input frequency to the output frequency:

$$\frac{{f}_{\text{in}}}{{f}_{\text{out}}}=(N+1)S+N(P-S)=NP+S$$

**Note**

To prevent the program counter and prescaler from resetting prematurely before the swallow counter finishes counting, the condition $$P\ge S$$ must be met.

The dual modulus prescaler is also known as pulse swallow divider.

[1] Razavi, Behzad. *RF
Microelectronics*. Upper Saddle River, NJ: Prentice Hall PTR,
1998.

Fractional Clock Divider with Accumulator | Fractional Clock Divider with DSM | PFD | Single Modulus Prescaler | VCO