After you generate HDL code from a MATLAB® design, you can cosimulate the design in ModelSim® or Cadence Incisive®. You can optionally generate a MATLAB test bench. To use this feature, you must have an HDL Coder™ license.
Start the MATLAB HDL Workflow Advisor.
At step HDL Verification, click Verify with Cosimulation.
Select Generate HDL test bench to instruct HDL Coder to generate HDL test bench code from your MATLAB test script (optional).
Select Log outputs for comparison plots if you would like to log and plot outputs of the reference design function and HDL simulator (optional).
For Cosimulate for use with, select either
Mentor Graphics ModelSim or
Incisive as the HDL simulator you want for
For HDL simulator run mode in cosimulation, select
Batch mode for non-interactive simulation. Select
GUI mode to view waveforms.
Select Simulate generated cosimulation test bench to automatically verify the generated HDL code in a cosimulation test bench.
For Advanced Options, select and set the optional parameters according to the descriptions in the following table.
|Clock high time (ns)||Specify the number of nanoseconds the clock is high.|
|Clock low time (ns)||Specify the number of nanoseconds the clock is low.|
|Hold time (ns)||Specify the hold time for input signals and forced reset signals.|
|Clock enable delay (in clock cycles)||Specify time (in clock cycles) between deassertion of reset and assertion of clock enable.|
|Reset length (in clock cycles)||Specify time (in clock cycles) between assertion and deassertion of reset.|
Optionally, select Skip this step if you don’t want to verify with cosimulation.
If you selected Batch mode, a command window appears to launch the HDL simulator and run the cosimulation. This window is closed programmatically. If you selected GUI mode, the HDL simulator is opened and left open after simulation so that you may examine the waveforms and other signal data.
If there are errors, those messages appear in the message pane. Correct any errors and click Run.