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Use HDL Parameters in Cosimulation

You can configure Verilog or VHDL parameters in a cosimulation. When you use the Cosimulation Wizard to generate an HDL Cosimulation block or an hdlverifier.HDLCosimulation System object™, the Simulation Options step creates a configuration file named parameter_DUT.cfg, where DUT is the name of your HDL DUT. The configuration file includes a line for each HDL parameter, with a default value assigned. Uncomment the line for the parameter you want to configure and assign a value to override the default value.

For example, consider this generated configuration file, generated for ModelSim® cosimulation.

# Uncomment lines below for any parameter whose default value you want to change.
# For parameters marked "N/A" (not available) the default value could not be 
# determined, but you can override in the same way.

#-G/design_top/coeff1=0
#-G/design_top/coeff2=18
#-G/design_top/coeff3=74

To change the value of coeff1 to 32, uncomment that line and assign a value of 32.

-G/design_top/coeff1=32
#-G/design_top/coeff2=18
#-G/design_top/coeff3=74

Similarly, when you cosimulate with Xcelium™, the parameters in the configuration file are created with the -gpg directive to force value assignment for generics and parameters. 

-gpg "design_top.coeff1=120
#-gpg "design_top.coeff2=18
#-gpg "design_top.coeff3=74

This feature is not supported for Vivado® cosimulation

Supported Data Types

Supported Verilog data types

  • Integer — Up to 32 bit

  • Real

  • String — Up to 256 byte

Supported VHDL data types

  • Integer

  • Real

  • String — Up to 256 byte

  • Time

  • Bit

  • Boolean

  • Enum

  • std_logic

Cosimulation with Parameterized Port Size

In a Simulink® cosimulation, if your HDL design includes a parameter that configures the width of an input or an output port, the Cosimulation Wizard creates an HDL Cosimulation block with the default value for that port width. After generating the block, if you override the default value and assign another value to that parameter, you must follow these steps:

  1. Edit the parameter_DUT.cfg file and override the parameter value to reflect the desired port width. For example, change the output_width parameter to 8: 

    -G/design_top/output_width=8

  2. Make sure that the HDL simulator is not open. In the Simulink canvas that opens after generating the HDL Cosimulation block, double-click the block labeled Compile HDL Design to recompile the HDL design. Then, double-click the block labeled Launch HDL Simulator to start the HDL simulator.

    Simulink canvas open with the generated HDL Cosimulation block. Two blocks are highlighted: Compile HDL Design and Launch HDL Simulator.

  3. After the HDL simulator opens and loads the design, open the HDL Cosimulation block mask. On the Ports tab, select each port and click Delete until the table is empty.

  4. Click Auto Fill and, in the Auto Fill pane that opens, enter the path to the DUT.

    HDL Cosimulation block mask open on the Ports tab. The ports are deleted, and the 'Auto Fill' button is highlighted.

  5. Click Fill. The port list reflects the new parameter value.

    This port list includes the HDL ports with the modified port widths, as well as ports for clock and reset. Since Simulink has an implicit clock and reset, you can select and remove those two ports from the list.

  6. Continue cosimulation activities. Do not regenerate the block.

See Also

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