Getting Started with Filter Design HDL Coder

Generate HDL code for fixed-point filters

Filter Design HDL Coder™ generates synthesizable, portable VHDL® and Verilog® code for implementing fixed-point filters designed with MATLAB® on FPGAs or ASICs. It automatically creates VHDL and Verilog test benches for simulating, testing, and verifying the generated code.

Tutorials

  • Basic FIR Filter

    Design a basic quantized discrete-time FIR filter, generate VHDL code for the filter, and verify the VHDL code with a generated test bench.

  • Optimized FIR Filter

    Design an optimized FIR filter, generate Verilog code for the filter, and verify the Verilog code with a generated test bench.

  • IIR Filter

    Design an IIR filter, generate VHDL code for the filter, and verify the VHDL code with a generated test bench.

About Filter Design and HDL Code Generation

Featured Examples