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Enable Readback on AXI4 Slave Input Registers to Inspect Written Values

This example describes the different techniques to read the AXI4 slave input registers in your design. It shows the process of how to enable readback on AXI4 slave input registers and read the values of AXI4 slave input registers for your design.

Introduction

You can select the AXI4 or AXI4-Lite interface in the IP core generation or Simulink Real-Time FPGA I/O workflow in HDL Workflow Advisor. By default, your IP will be generated without the readback capability of the AXI4 or AXI4-Lite input registers. When the readback feature is enabled from HDL Workflow Advisor or from command line interface, you can read the values of input registers. This is very useful technique for debugging the input values which are written into AXI4 or AXI4-Lite interface. The figure shows the AXI4 slave interface and its registers.

Enabling AXI4 Slave Input Register Readback

1. Readback of AXI4 slave registers can be performed when your design contains AXI4 or AXI4-Lite interface. You can use any model which has these interface. Use hdlcoder_led_blinking or hdlcoder_led_blinking_4bit model. Open the Simulink model that implements LED blinking using the command,

open_system('hdlcoder_led_blinking');

2. Run all the Tasks till Task 3.1, Set HDL Options.

3. Readback on AXI4 slave input registers can be turned ON by using HDL workflow Advisor or using command line interface. In Task 3.2, Generate RTL Code and IP Core, by default readback on AXI4 slave input register is turned OFF. To enable this option, select Enable readback on AXI4 slave write registers in Task 3.2 Generate RTL Code and IP Core of HDL Workflow Advisor.

You can also enable the readback option in MATLAB command line interface by using hdlset_param function. The figure shows the command to set 'AXI4RegisterReadback' parameter in hdlset_param. The default value is 'off'.

Read Values of the AXI4 Slave input registers

After setting the readback option for your model, Generate RTL code and IP Core using Task 3.2 option in HDL Workflow Advisor or through command line interface. Once IP core is generated, IP Core Generation Report is generated in the code generation report. IP Core Generation Report contains the details about Target Platform Interface of your model. The figure shows the AXI-Lite interface mapped to the hdlcoder_led_blinking model ports. The table in IP Core Generation Report shows the interface mapping address of each AXI4 slave register. These addresses are used to read the AXI4 slave input registers.

The AXI4 slave base address is used together with interface mapping address to read the value of AXI4 slave input registers. These address mapping details are used to read the AXI4 slave registers. Readback of input registers can be performed in three ways.

1. Using MATLAB FPGA Prototyping API Script

2. Using JTAG MATLAB as AXI Master

3. Using Devmem command to probe the registers from target

To read the value, you can use any of the above techniques. After that you must complete all the steps in HDL Workflow Advisor. Once bitstream is generated and programmed into the target device, perform readback of input registers.

Readback of AXI4 Slave Input Registers Using MATLAB FPGA Prototyping API Script

AXI4 Slave input registers can be read using MATLAB FPGA prototyping API scripts. Once RTL Code and IP core is generated, MATLAB Software interface scripts can be generated in Task 4.2 Generate Software Interface from HDL Workflow Advisor. The option Generate MATLAB software interface scripts generates the MATLAB prototyping API scripts. See figure below.

This option generates two scripts, that are interface and setup scripts which is as shown below for hdlcoder_led_blinking_4bit model.

The setup function contains commands for the AXI4 slave interfaces that HDL Coder uses to control the DUT ports in the generated HDL IP core that are mapped to the corresponding interfaces.

The software interface script instantiates this setup function to connect to the target and send read or write commands. You can uncomment and send meaningful data by using the inputs to the DUT in your original model. After interfacing with the hardware, the script disconnects from the hardware resource associated with the FPGA object.

Now generate the bitstream and program the target device. In order to write and read the data for blink_frequency, modify the interface script as shown below and run the script. You can see that value 10 is written to the blink_frequency and axi4read shows the readback of blink_frequency.

MATLAB prototyping API uses JTAG MATLAB as AXI Master for readback of AXI4 slave input registers. For more details, see Generate Software Interface Script to Probe and Rapidly Prototype HDL IP Core.

Readback of AXI4 Slave Input Registers using JTAG MATLAB as AXI Master.

JTAG MATLAB as AXI Master can also be used separately for readback of AXI4 slave input registers. To use JTAG MATLAB as AXI Master, JTAG MATLAB as AXI Master IP must be inserted into reference design. The figure shows the Task 1.2 Set Target Reference Design of HDL Workflow Advisor to set insert JTAG MATLAB as AXI Master in your reference design.

Now set the necessary options for enabling readback as mentioned in earlier section and follow the example Using JTAG MATLAB as AXI Master to control HDL Coder generated IP Core for more details.

Readback of AXI4 Slave Input Registers Using Devmem Command (Probe Registers from Target)

Devmem command can be used in Putty or Hyper Terminal. Once the bitstream is programmed into the target device, open Putty or hyper terminal using serial interface. To use devmem command for the hdlcoder_led_blinking model use these steps.

1. Read the data from address '400D0100' using following command.

   devmem 0x400D0100

you will get the value as 0x00000000

2. Write some value in address '400D0100' using following command.

   devmem 0x400D0100 w 0x1

3. Again read the address '400D0100'.

  devmem 0x400D0100

Now you will get value as 0x00000001. For more details see the figure below.

In this way scalars can be read. In the vector data type, you first need to write the data on the register and then write 0x1 to the strobe address as in vector mode strobe synchronization is done for writing. After writing on strobe address customer reads the data on register using same address. The figure shows the writing and reading of the values in the vector data type using devmem.

1. Try to read the address 0x400D0100 and 0x400D0104 which shows as 0 as nothing is written in those registers.

2. Try writing 0x2 on address 0x400D0100 and then write 0x1 on strobe address 0x400D0110.

3. Now read the data on address 0x400D0100 and it shows as 0x00000002.

4. Similarly write 0x3 on address 0x400D0104 and then write 0x1 on strobe address 0x400D0110.

5. Now read the data on address 0x400D0104 and it shows 0x00000003.

Using AXI4 Slave Port to Pipeline Register Ratio.

This is an additional option to optimize your design to meet desired Frequency. When you have considerable number of AXI4 slave input ports in the design and AXI4 slave readback of input register is turned on, the design becomes complex and you might not get desired timing requirements. To optimize the readback capability of the AXI4 slave input registers, pipelined registers can be inserted for number of AXI4 slave ports. You can set AXI4 slave port to pipeline register ratio option from HDL Workflow Advisor, Command Line Interface or from HDL Block properties of the DUT subsystem. The figure shows the HDL Workflow Advisor for Task 3.2 to set AXI4 slave port to pipeline register ratio option.

The table shows the drop-down options available in AXI4 slave port to pipeline ratio

You can also set this option in MATLAB command line interface by using hdlset_param function. The figure shows the command to set 'AXI4SlavePortToPipelineRegisterRatio' parameter in hdlset_param. The default value is 'auto'.

To select this option using HDL Block properties, right click on DUT subsystem and select HDL Code > HDL Block Properties. See figure below.

In HDL Block Properties, chose Target Specification tab and set 'AXI4SlavePortToPipelineRegisterRatio' in IP Core Parameter section. See figure below.

Once you set the AXI4 slave port to pipeline register ratio using one of the above options, you can follow the steps for the readback mentioned in section Read Values of the AXI4 Slave input registers.