Model referencing in your DUT subsystem enables you to:
Partition a large design into a hierarchy of smaller designs for reuse, modular development, and accelerated simulation.
Incrementally generate and test code.
HDL Coder™ incrementally generates code for referenced models according to the Configuration Parameters dialog box > Model Referencing pane > Rebuild options.
However, HDL Coder treats
If any changes detected and
any changes in known dependencies detected as the same.
For example, if you set Rebuild to either
any changes detected or
If any changes
in known dependencies detected, HDL Coder regenerates
code for referenced models only when the referenced models have changed.
By default, Generate VHDL code for model references into a single library is enabled. The VHDL code is generated in a single
library instead of separate libraries. In this case, set the
ScalarizePorts property to
off before generating
When generating code, if you encounter typing or naming conflicts between vector ports
when interfacing two or more generated VHDL® code modules, use the
ScalarizePorts property to generate
non-conflicting port definitions. For more information, see Scalarize ports.
You can generate HDL code for the referenced model using the UI or the command line.
Right-click the Model block and select HDL Code > HDL Block Properties.
For Architecture, select ModelReference.
Generate HDL code from your DUT subsystem.
Architecture property of the Model block to
ModelReference. For example, for a DUT subsystem,
mydut, that includes a model reference,
referenced_model, enter this
hdlset_param ('mydut/referenced_model', ... 'Architecture', 'ModelReference');
Generate HDL code for your DUT subsystem.
To generate a single Verilog®
module or VHDL
entity for instances of a referenced model with different model argument
values, see Generate Parameterized Code for Referenced Models.
If you enter text in the Model Block Properties dialog box Description field, HDL Coder generates a comment in the HDL code.
Model block must have default values for the Block parameters.
Model block cannot be a masked subsystem.
Multiple model references that refer to the same model must have the same HDL block properties.
Referenced models cannot be protected models.
Hierarchical distributed pipelining must be disabled.
HDL Coder cannot move registers across a model reference. Therefore, referenced models can inhibit these optimizations:
Constrained output pipelining
When you have model references and generate HDL code, the generated model, validation model, and cosimulation model can fail to compile or simulate. To fix compilation or simulation errors, make sure that the referenced models are loaded or are on the search path.
The coder can apply the resource sharing optimization to share referenced model instances. However, you can apply this optimization only when all model references that point to the same referenced model have the same rate after optimizations and rate propagation. The model reference final rate may differ from the original rate, but all model references that point to the same referenced model must have the same final rate.