Generate HDL and HLS Code from a Symmetric FIR Filter Using System Objects

R2026b

This example shows how to generate HDL and HLS code from a MATLAB^® function that implements a symmetric FIR filter. The design uses dsp.Delay (DSP System Toolbox) System objects to model filter state and exploits coefficient symmetry to reduce the number of multiplications.

FIR filters are fundamental building blocks in digital signal processing for applications such as noise reduction, channel equalization, and spectral shaping. A symmetric FIR filter takes advantage of the fact that its coefficients are mirrored, halving the required multiplications and making the design more efficient for hardware.

Examine the MATLAB Design and Test Bench

Set up the MATLAB function and test bench for this example. In the MATLAB Command Window, enter:

mlhdlc_demo_setup("mlhdlc_sysobj_ex");

This command opens a temporary working folder with the files required to run this example. The folder includes the:

• MATLAB function

• Test bench

• <model>_runme.m script, which includes the commands to generate HDL code

• <model>_runme_hls.m script, which includes the commands to generate HLS code

The MATLAB function, mlhdlc_sysobj_ex, accepts a data sample and four filter coefficients as inputs. It uses eight persistent dsp.Delay System objects to model an 8-tap delay line, pairs symmetric taps to reduce multiplications from eight to four, and returns the filtered output and the delayed input signal.

To view the function, enter:

open mlhdlc_sysobj_ex.m;

The test bench file, mlhdlc_sysobj_ex_tb, verifies the behavior of the MATLAB function. It generates a chirp signal with increasing frequency and feeds samples one at a time to the design with fixed coefficients to verify the filtering behavior. To view the test bench, enter:

open mlhdlc_sysobj_ex_tb;

Simulate the Design

To check for run-time errors, simulate the design by running the test bench. In the MATLAB Command Window, enter:

mlhdlc_sysobj_ex_tb;

Generate HDL Code

The mlhdlc_sysobj_ex_runme script specifies the target files, enables the settings required for this example, and generates HDL code.

The script specifies the MATLAB function and test bench, then creates a fixed-point configuration object and an HDL configuration object by using the coder.config function. The script associates the test bench with both configuration objects.

designName = "mlhdlc_sysobj_ex";
designTB = "mlhdlc_sysobj_ex_tb";
fixptCfg = coder.config("fixpt");
fixptCfg.TestBenchName = designTB;
cfg = coder.config("hdl");
cfg.TestBenchName = designTB;

The script specifies the synthesis tool, chip family, device name, package name, and speed value:

cfg.SynthesisTool = "Xilinx Vivado";
cfg.SynthesisToolChipFamily = "Artix7";
cfg.SynthesisToolDeviceName = "xa7a100t";
cfg.SynthesisToolPackageName = "csg324";
cfg.SynthesisToolSpeedValue = "-1I";

The script then generates code:

codegen("-float2fixed", "fixptCfg", "-config", "cfg", designName, ...
"-launchreport");

Run the Script

First, modify the mlhdlc_sysobj_ex_runme script. The script disables synthesis by default. Set the value for the SynthesizeGeneratedCode property to true:

cfg.SynthesizeGeneratedCode = true;

Update the settings for your synthesis tool:

cfg.SynthesisTool = "Xilinx Vivado";
cfg.SynthesisToolChipFamily = "Artix7";
cfg.SynthesisToolDeviceName = "xa7a100t";
cfg.SynthesisToolPackageName = "csg324";
cfg.SynthesisToolSpeedValue = "-1I";

Then, generate code by running the script:

mlhdlc_sysobj_ex_runme

After code generation completes, the report opens. Examine the generated HDL code in the report.

Generate HLS Code

The mlhdlc_sysobj_ex_runme_hls script specifies the target files, enables the settings required for this example, and generates HLS code.

The script specifies the MATLAB function and test bench, then creates a fixed-point configuration object and an HLS configuration object by using the coder.config function. It associates the test bench with both configuration objects.

designName = "mlhdlc_sysobj_ex";
designTB = "mlhdlc_sysobj_ex_tb";
fixptCfg = coder.config("fixpt");
fixptCfg.TestBenchName = designTB;

The script creates an HLS configuration object by using the coder.config function, associates the test bench, and enables simulation.

cfg = coder.config("hls");
cfg.TestBenchName = designTB;
cfg.GenerateHLSTestBench = true;
cfg.SimulateGeneratedCode = true;

The script specifies the synthesis tool, chip family, device name, package name, and speed value:

cfg.SynthesisTool = "Xilinx Vitis HLS";
cfg.SynthesisToolChipFamily = "Artix7";
cfg.SynthesisToolDeviceName = "xa7a100t";
cfg.SynthesisToolPackageName = "csg324";
cfg.SynthesisToolSpeedValue = "-1I";

The script then generates code:

codegen("-float2fixed", "fixptCfg", "-config", "cfg", designName, ...
"-launchreport");

Run the Script

First, modify the mlhdlc_sysobj_ex_runme_hls script. The script disables synthesis by default. Set the value for the SynthesizeGeneratedCode property to true:

cfg.SynthesizeGeneratedCode = true;

Depending on your synthesis tool, set one of these flags to true:

isCodingForStratusHLS = false;
isCodingForVitisHLS = true;

Depending on your synthesis tool, update these synthesis tool settings:

if isCodingForStratusHLS
    cfg.SynthesisTool = "Cadence Stratus HLS";
elseif isCodingForVitisHLS
    cfg.SynthesisTool = "Xilinx Vitis HLS";
    cfg.SynthesisToolChipFamily = "Artix7";
    cfg.SynthesisToolDeviceName = "xa7a100t";
    cfg.SynthesisToolPackageName = "csg324";
    cfg.SynthesisToolSpeedValue = "-1I";
end

Then, generate code by running the script:

mlhdlc_sysobj_ex_runme_hls

After code generation completes, the report opens. Examine the generated HLS code in the report.