Generate HDL and HLS Code from Ring Buffer Designs Using RAM
R2026bThis example shows how to generate HDL and HLS code from MATLAB® functions that model a ring buffer using RAM. The example demonstrates two
approaches: using the hdl.RAM
Ring buffers are common in signal and image processing pipelines where data must be delayed by a fixed number of clock cycles, such as line delays in video processing or FIR filter implementations. Hardware implementations map these delay structures to on-chip block RAM for area efficiency.
Examine the MATLAB Designs and Test Bench
Set up the MATLAB functions and test bench for this example. In the MATLAB Command Window, enter:
mlhdlc_demo_setup("mlhdlc_hdlram");Two MATLAB functions (explicit and implicit RAM designs)
Test bench
<model>_runme_hdl.mscript, which includes the commands to generate HDL code<model>_runme_hls.mscript, which includes the commands to generate HLS code
The first MATLAB function, mlhdlc_hdlram_explicit, accepts a
data sample and writes it to a dual-port RAM at an offset address using the
hdl.RAM System object. It reads from the current address to
produce the delayed output. This approach gives direct control over RAM port
configuration. To view the function,
enter:
open mlhdlc_hdlram_explicit.m;The second MATLAB function, mlhdlc_hdlram_implicit, implements
the same ring buffer behavior using a 256-element persistent array. HDL Coder infers
this array as block RAM during code generation because the array size exceeds the
RAM mapping threshold. To view the function,
enter:
open mlhdlc_hdlram_implicit.m;The test bench file, mlhdlc_hdlram_tb, feeds 100 samples to
both design functions and plots the input alongside the delayed outputs from each
approach to verify that both produce the same ring buffer delay. To view the test
bench,
enter:
open mlhdlc_hdlram_tb.m;Simulate the Design
To check for run-time errors, simulate the design by running the test bench. In the MATLAB Command Window, enter:
mlhdlc_hdlram_tb;
Generate HDL Code
The mlhdlc_hdlram_runme_hdl script specifies the target files,
enables the settings required for this example, and generates HDL code for both
design functions.
The script specifies the two MATLAB functions and the test bench, then creates a
fixed-point configuration object and an HDL configuration object by using the
coder.config function. It associates the test bench with
both configuration
objects.
designName1 = "mlhdlc_hdlram_implicit"; designName2 = "mlhdlc_hdlram_explicit"; designTB = "mlhdlc_hdlram_tb"; fixptCfg = coder.config("fixpt"); fixptCfg.TestBenchName = designTB; cfg = coder.config("hdl"); cfg.TestBenchName = designTB;
The script specifies the synthesis tool, chip family, device name, package name, and speed value:
cfg.SynthesisTool = "Xilinx Vivado"; cfg.SynthesisToolChipFamily = "Artix7"; cfg.SynthesisToolDeviceName = "xa7a100t"; cfg.SynthesisToolPackageName = "csg324"; cfg.SynthesisToolSpeedValue = "-1I";
The script then generates code for both designs:
codegen("-float2fixed", "fixptCfg", "-config", "cfg", designName1, ... "-launchreport"); codegen("-float2fixed", "fixptCfg", "-config", "cfg", designName2, ... "-launchreport");
Run the Script
First, modify the mlhdlc_hdlram_runme_hdl script. The
script disables synthesis by default. Set the value for the
SynthesizeGeneratedCode property to
true:
cfg.SynthesizeGeneratedCode = true;
Update the settings for your synthesis tool:
cfg.SynthesisTool = "Xilinx Vivado"; cfg.SynthesisToolChipFamily = "Artix7"; cfg.SynthesisToolDeviceName = "xa7a100t"; cfg.SynthesisToolPackageName = "csg324"; cfg.SynthesisToolSpeedValue = "-1I";
Then, generate code by running the script:
mlhdlc_hdlram_runme_hdl
After code generation completes, the report opens. Examine the generated HDL code in the report.
Generate HLS Code
The mlhdlc_hdlram_runme_hls script specifies the target files,
enables the settings required for this example, and generates HLS code for both
design functions.
The script specifies the two MATLAB functions and the test bench, then creates a
fixed-point configuration object by using the coder.config
function. It associates the test bench with the configuration
object.
designName1 = "mlhdlc_hdlram_implicit"; designName2 = "mlhdlc_hdlram_explicit"; designTB = "mlhdlc_hdlram_tb"; fixptCfg = coder.config("fixpt"); fixptCfg.TestBenchName = designTB;
The script creates an HLS configuration object by using the
coder.config function, associates the test bench, and
enables
simulation.
cfg = coder.config("hls");
cfg.TestBenchName = designTB;
cfg.GenerateHLSTestBench = true;
cfg.SimulateGeneratedCode = true;The script specifies the synthesis tool, chip family, device name, package name, and speed value:
cfg.SynthesisTool = "Xilinx Vitis HLS"; cfg.SynthesisToolChipFamily = "Artix7"; cfg.SynthesisToolDeviceName = "xa7a100t"; cfg.SynthesisToolPackageName = "csg324"; cfg.SynthesisToolSpeedValue = "-1I";
The script then generates code for both designs:
codegen("-float2fixed", "fixptCfg", "-config", "cfg", designName1, ... "-launchreport"); codegen("-float2fixed", "fixptCfg", "-config", "cfg", designName2, ... "-launchreport");
Run the Script
First, modify the mlhdlc_hdlram_runme_hls script. The
script disables synthesis by default. Set the value for the
SynthesizeGeneratedCode property to
true:
cfg.SynthesizeGeneratedCode = true;
Depending on your synthesis tool, set one of these flags to
true:
isCodingForStratusHLS = false; isCodingForVitisHLS = true;
Depending on your synthesis tool, update these synthesis tool settings:
if isCodingForStratusHLS cfg.SynthesisTool = "Cadence Stratus HLS"; elseif isCodingForVitisHLS cfg.SynthesisTool = "Xilinx Vitis HLS"; cfg.SynthesisToolChipFamily = "Artix7"; cfg.SynthesisToolDeviceName = "xa7a100t"; cfg.SynthesisToolPackageName = "csg324"; cfg.SynthesisToolSpeedValue = "-1I"; end
Then, generate code by running the script:
mlhdlc_hdlram_runme_hls
After code generation completes, the report opens. Examine the generated HLS code in the report.
