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Single Port RAM

Single port RAM


HDL Coder / HDL RAMs

  • Single Port RAM block


The Single Port RAM block models RAM that supports sequential read and write operations.

If you want to model RAM that supports simultaneous read and write operations, use the Dual Port RAM or Simple Dual Port RAM.


Address port width

Address bit width. Minimum bit width is 2, and maximum bit width is 29. The default is 8.

Output data during write

Controls the output data, dout, during a write access.

  • New data (default): During a write, new data appears at the output port, dout.

  • Old data: During a write, old data appears at the output port, dout.


The block has the following ports:


Data input. The data can have any width. It inherits the width and data type from the input signal.

Data type: scalar fixed point, integer, or complex


Write address.

Data type: scalar unsigned integer (uintN) or unsigned fixed point (ufixN) with a fraction length of 0


Write enable.

Data type: Boolean


Output data from address, addr.


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HDL code generated for RAM blocks has:

  • A latency of one clock cycle for read data output.

  • No reset signal, because some synthesis tools do not infer a RAM from HDL code if it includes a reset.

Code generation for a RAM block creates a separate file, blockname.ext. blockname is derived from the name of the RAM block. ext is the target language file name extension.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Introduced in R2014a