White Paper

Wireless Prototyping and Production Development

Top-Down Collaboration

Bring together multiple skill sets early in the process

With the growth of wireless standards and infrastructure, new systems and hardware must be developed under a rapid timeline. Traditional workflows that divide responsibilities and rely on specification documents prevent the type of multidiscipline collaboration needed to deliver novel products on schedule.

Key Takeaways

  • Enable collaboration between multiple domain experts
  • Simulate system-level behavior to detect and eliminate costly issues early
  • Improve quality through broader architecture exploration

Learn More About Model-Based Design

  • Adopting Model-Based Design for FPGA, ASIC, and SoC Development

FPGA Prototyping Without VHDL/Verilog Expertise

Target and debug FPGA prototype hardware directly from MATLAB and Simulink

Prototyping wireless communications algorithms on FPGA or software-defined radio (SDR) hardware platforms delivers early insight to performance in realistic operating conditions, and often serves as a key demonstration checkpoint as the project progresses toward production development. Where traditional prototyping workflows place a heavy burden on scarce hardware design engineers, using MATLAB® and Simulink® enables communications and DSP engineers to be more self-sufficient in creating and debugging FPGA prototypes. This approach results in faster iterations and getting to a working prototype with less time and effort.

After modeling and simulating your system-level algorithms, you can incrementally add live prototype hardware elements. Start by connecting MATLAB and Simulink to the prototype transceiver to simulate with live over-the-air input/output. Even when deploying to the prototype device, you can stay connected to MATLAB and Simulink for analysis and debug before full field testing. You can get started quickly using the Communications Toolbox™ Support Package for Xilinx® Zynq®-Based Radio or build this capability yourself for your custom board.

While there are no shortcuts to targeting FPGA hardware, guidance and automation make it more attainable. Fixed-Point Designer™ automates the quantization process to help you balance efficiency versus accuracy. The HDL Coder™ Workflow Advisor manages the process from helping prepare your design for targeting all the way through FPGA implementation.

Prototyping introduces unanticipated real-world effects such as interference, which can cause the design to malfunction or perform more poorly than expected. You can use MATLAB and Simulink with HDL Verifier to analyze and debug these issues with the device connected directly or by capturing the over-the-air waveforms to use in simulation.

A diagram illustrating how I P generated by H D L Verifier and built into programming files lets F P G A engineers capture signals from hardware tests for viewing in MATLAB or use MATLAB to write to or read from registers and memories.

Key Takeaways

  • Iterate and get to a working prototype more quickly
  • Increase your capability to prototype on digital hardware
  • Analyze and debug from within MATLAB and Simulink

Request a Free Trial

  • Try HDL Coder for your next project prototyping on FPGA-based development kits.

Hardware-Proven Design IP

Speed your project schedule by using configurable hardware implementations of standards-based algorithms

Wireless communications rely heavily upon standard signal protocols, modulation/demodulation schemes, and error correction coding to ensure system and device interoperability. In most cases, this standard functionality does not differentiate your application, but you still need to integrate it into your FPGA or ASIC. Using proven intellectual property (IP) saves your engineers’ time and effort so they can focus on developing and implementing your unique functionality.

A diagram depicting how the outputs of a block containing a behavioral MATLAB model could be compared to the outputs from the hardware implementation of that model.

Key Takeaways

  • Save hardware design and verification time and effort by using proven IP
  • Focus your hardware engineering resources on your unique functionality
  • Verify, adjust, and generate code from high-abstraction wireless design IP

Learn More

  • Explore the reference applications and design IP blocks in Wireless HDL Toolbox.

Code Generation for Hardware Design and Verification

Explore and simulate hardware architecture, then automatically generate project-specific RTL and verification components

Relying on specification documents to communicate functional intent exposes risks from oversights and assumptions and makes it difficult to adapt to changes. A top-down workflow refines the high-level algorithms with hardware implementation architecture, enabling easy exploration of more options, followed by high-level verification. From there you can directly generate code and models to begin production hardware design and verification.

Collaboration Between Algorithm and Hardware Engineers

Hardware engineers can collaborate with communications and DSP engineers in a visual environment to adapt their algorithms with parallelism, timing, and fixed-point quantization to map efficiently to hardware while producing sufficiently accurate results. The result is an easy-to-follow simulation model from which you can generate code for downstream design and verification.

Target-Independent HDL Code Generation

After iterative refinement from algorithm to fixed-point hardware architecture, you can automatically generate readable and synthesizable VHDL® or Verilog® RTL. Customize the RTL for your project requirements and target device and adapt to changes with agility.

SystemVerilog Verification Component Generation

You can start connecting algorithm and hardware development by generating SystemVerilog DPI or UVM verification components from MATLAB or Simulink algorithms and tests. Automatic verification model generation enables changes in the digital algorithms to be quickly updated for simulation in analog implementation, and vice versa.

“We have improved communication between teams, reduced development time, and reduced risk by evaluating system performance early in the design process.”


Key Takeaways

  • Improve quality by exploring a broad range of hardware architecture options
  • Quickly adapt to changes and regenerate code for new requirements
  • Generate models to speed verification environment creation

Learn More About Code Generation

  • Generate a 5G waveform for SystemVerilog verification.