Reference Design Integration and Deployment

Integrate the generated IP core into the default system reference design

You can integrate the generated IP core into the default system reference design or into your own custom reference design that you register for the board. HDL Coder™ can generate an IP core, integrate it into your Vivado^® project, and program the hardware. Using Embedded Coder^®, you can generate and build the embedded software, and run it on the ARM^® processor.

Topics

Default System Reference Design for Xilinx SoC Device
Learn about the default system reference design for Xilinx^® SoC device and using the reference design.
Default System Reference Design for Xilinx FPGA Board
Learn about the default system reference design for Xilinx FPGA board and using the reference design.
Default System with AXI4-Stream Interface Reference Design
Learn about how to use the default system with AXI4-Stream Interface reference design and its requirements.
Default Video System Reference Design
Learn about the default video system reference design and its requirements.
Default System with External DDR Memory Access Reference Design
Learn about the default system with external DDR3 memory access reference design and its requirements.
Program Target FPGA Boards or SoC Devices
How to program the target Intel or Xilinx Hardware.

Featured Examples

Running an Audio Filter on Live Audio Input Using a Zynq Board

Model an audio system and implement it on a Zynq® board using an audio reference design.

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Debug a Zynq Design Using HDL Coder and Embedded Coder

Debug a Zynq® design using HDL Coder™ and Embedded Coder® features.

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Debug IP Core Using FPGA Data Capture

Debug an IP core you generate in HDL Coder™ using only FPGA Data Capture as well as both AXI Manager and FPGA Data Capture together.

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Access DUT Registers on Xilinx Pure FPGA Board Using IP Core Generation Workflow

Use the HDL Coder™ IP core generation workflow to develop reference designs for Xilinx® parts that do not use an embedded ARM® processor present but that still utilize the HDL Coder generated AXI interface to control the design under test (DUT). This example uses the HDL Verifier™ AXI Manager IP to access the HDL Coder generated DUT registers from MATLAB®. Alternatively, you can use the Xilinx JTAG AXI Master to access the DUT registers using Vivado® Tcl console by writing Tcl commands. For the Xilinx JTAG AXI Master, you must create a custom reference design. The FPGA design is implemented on the Xilinx Kintex®-7 KC705 board.

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