Eric Cigan, MathWorks
Performing interactive testing on FPGA and SoC FPGA boards is a popular way to verify designs and perform parametric testing. See how HDL Verifier™ lets you to control interactive testing on Intel® FPGA boards directly from your MATLAB® session.
The MATLAB as AXI Master feature of HDL Verifier gives you read/write access to on-board memory locations from MATLAB. You’ll see a demonstration of how to generate an IP core using HDL Coder™ to set it up for interactive testing and then how to use MATLAB commands to read from and write to AXI-accessible registers on an Intel MAX® 10 FPGA. The board used in the video is a DECA MAX10 FPGA Evaluation Kit from Arrow Electronics.
Finally, learn how to use a custom app created in MATLAB App Designer to serve as a control panel for hardware testing.
Choose a web site to get translated content where available and see local events and offers. Based on your location, we recommend that you select: .Select web site
You can also select a web site from the following list:
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location.