Design Verification with Simulink

This one-day course focuses on using Simulink Design Verifier to ensure that a design is devoid of possible design errors, is fully tested, and satisfies necessary requirements. Topics include:

  • Detecting and debugging common design errors
  • Collecting model coverage
  • Completing missing coverage using automatic test generation
  • Proving model properties for requirements-based verification
  • Handling model complexity for efficient analysis

See detailed course outline

MATLAB and Simulink Course Schedule

There are currently no scheduled classes for this course.