Identify and isolate design errors and generate tests

Simulink Design Verifier™ uses formal methods to identify hidden design errors in models without extensive simulation runs. It detects blocks in the model that result in integer overflow, dead logic, array access violations, division by zero, and requirement violations. For each error it produces a simulation test case for debugging.

Simulink Design Verifier generates test inputs for model coverage and custom objectives. It also lets you augment and extend existing test cases. These test cases drive your model to satisfy condition, decision, modified condition/decision (MCDC), and custom coverage objectives.

The Model Slicer tool in Simulink Design Verifier isolates problematic behavior in a model using a combination of dynamic and static analysis. It lets you highlight and trace functional dependencies of ports, signals, and blocks, and slice a large model into smaller, standalone models for analysis. You can view blocks affecting a subsystem output and trace a signal path through multiple switches and logic. The Variant Reducer tool enables you to simplify models containing multiple variants by creating sliced models based on active variant configurations.

Support for industry standards is available through IEC Certification Kit (for ISO 26262 and IEC 61508) and DO Qualification Kit (for DO-178).

Verifying Models and Code for High-Integrity Systems


Design Error Detection

Discover whether specific dynamic execution scenarios can occur and under what conditions.

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Test Case Input Generation

Use structural verification techniques such as model coverage to help identify unused simulation pathways in the model.

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Isolating Problematic Behavior with Model Slicer

Isolate behaviors of interest in a model using a combination of dynamic and static analysis to trace dependencies.

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Simplify Variant Systems with Variant Reducer

Create a simplified, standalone model containing only the active variant configuration.

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Requirements-Based Verification

Express formal requirements using MATLAB functions, Simulink, and Stateflow.

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Product Resources

Discover more about Simulink Design Verifier by exploring these resources.


Explore documentation for Simulink Design Verifier functions and features, including release notes and examples.


Browse the list of available Simulink Design Verifier functions.


View a Simulink library of blocks that Simulink Design Verifier supports.

System Requirements

View system requirements for the latest release of Simulink Design Verifier.

Technical Articles

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User Stories

Read how Simulink Design Verifier is accelerating research and development in your industry.

Community and Support

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Simulink Design Verifier requires: Simulink Check, MATLAB, Simulink Coverage, Simulink

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News and Events

This presentation introduces Simulink Verification and Validation and Simulink Design Verifier. It highlights advanced verification and validation techniques (involving structural coverage analysis and formal methods) for testing various components

Increasing Robustness of your Software Designs with Simulink