Version 3.11, part of Release 2017b, includes the following enhancements:

  • Model Advisor Checks: Check and update your Simulink model for HDL code generation compatibility
  • Vector Input Multiply-Accumulate (MAC) Block: Map arithmetic operations efficiently to FPGA DSP slices
  • Minimum Resource FFT/IFFT: Reduce resource usage with the Burst Radix 2 architecture of the HDL-Optimized FFT (requires DSP System Toolbox)
  • AXI4 Master Interface: Facilitate communication between your design and external memory by using the AXI4 Master protocol for more flexible data access
  • Simulink Test Points in HDL: Debug internal signals by automatically routing the signals to top-level HDL ports

See the Release Notes for details.

Version 3.10, part of Release 2017a, includes the following enhancements:

  • For Each Subsystems: Reduce block replication and improve code reuse in HDL-targeted designs
  • Data Type Support for AXI4 Slave: Map floating-point signals and vector signals to AXI4 slave interfaces in IP core generation
  • HDL Floating Point Operations Library: Easily find additional and existing single-precision floating-point blocks supported for HDL code generation
  • Incremental Vivado Synthesis: Enable IP caching for faster synthesis of Xilinx Vivado reference designs
  • HDL Optimized Filters: Model and generate optimized hardware implementations for FIR filters (requires DSP System Toolbox)​
  • HDL Channelizer Block and System Object: Isolate narrowband channels from a wideband signal and generate HDL with efficient multiplier usage (requires DSP System Toolbox)​
  • Gigasample per Second (GSPS) Signal Processing: Increase throughput of FIR decimation algorithms by using frame input
  • Native Floating-Point Testbench: Generate SystemVerilog DPI, cosimulation, and FPGA-in-the-loop test benches with single-precision data types (requires HDL Verifier)

See the Release Notes for details.

Version 3.9, part of Release 2016b, includes the following enhancements:

  • Native Floating Point: Generate target-independent synthesizable RTL from single-precision floating-point models
  • Adaptive Pipelining: Specify synthesis tool and target clock frequency for automatic pipeline insertion and balancing
  • Logic Analyzer: Visualize, measure, and analyze transitions and states over time for Simulink signals

See the Release Notes for details.

Version 3.8, part of Release 2016a, includes the following enhancements:

  • Synchronous Subsystem Toggle: Specify enable and reset behavior for cleaner HDL code by using State Control block
  • Gigasample per Second (GSPS) Signal Processing: Increase throughput of HDL-optimized FFT and IFFT algorithms using frame input
  • Hard Floating-Point IP Targeting: Generate HDL to map to Intel Arria 10 floating-point units at user-specified target frequency
  • Resource Sharing Enhancements: Share multipliers and gain operations that have different data types
  • Faster Test Bench Generation and HDL Simulation: Generate SystemVerilog DPI test benches for large data sets with HDL Verifier

See the Release Notes for details.

Version 3.6.1, part of Release 2015aSP1, includes bug fixes.

See the Release Notes for details.

Version 3.7, part of Release 2015b, includes the following enhancements:

  • Tunable Parameters: Map Tunable Parameters to AXI4 Interface with HDL Coder 2:08
  • Expanded Bus Support: Generate HDL for enabled or triggered subsystems with bus inputs and for black boxes with bus I/O
  • Quality of Results Improvement: Stream and share resources more broadly and efficiently
  • Model Arguments: Parameterize instances of model reference blocks
  • End-to-end scripting from design through IP core generation, FPGA Turnkey, and generic ASIC/FPGA workflows

See the Release Notes for details.