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AriF


Last seen: mer än ett år ago Active since 2022

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Why do I get the error: " FIL cosimulation failed: the output does not match the expeced result" when I run FPGA-in-the-Loop Test?
Hi, iI m trying to run the fpga in the loop test inside HDL coder. The HDL code was generated by a script in matlab (I didn't us...

mer än ett år ago | 1 answer | 0

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