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Eric Cigan


MathWorks

10 total contributions since 2014

I joined MathWorks in 2007, where I am a member of the MathWorks team in Natick, Massachusetts that supports HDL code generation and verification.
Professional Interests: fpga, soc, signal processing, control design

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Answered
is it possible to run the demo "Performing Large Matrix Operation on FPGA using External Memory" on Intel Altera FPGA?
Yes, it should be possible. If you are still interested, please write to me at eric.cigan at mathworks.com.

mer än ett år ago | 0

| accepted

Answered
MATLAB and ModelSim, version compatibility
Here is a <https://www.mathworks.com/help/hdlverifier/gs/supported-eda-tools.html#bt16i4l-7 page that lists the versions of Mode...

mer än 2 år ago | 0

Answered
Vivado build in Simualtor co-simulation
We maintain a <https://www.mathworks.com/help/hdlverifier/gs/supported-eda-tools.html complete list of HDL simulators> for which...

mer än 2 år ago | 0

| accepted

Answered
Can I get a list of Altera FPGA boards supported by matlab/simulink?
[was a comment - re-submitting as an answer] At this point the DE1-SoC is not supported out of the box. However, it should be p...

mer än 2 år ago | 0

Answered
Compatibility for Mathworks' and Xilinx tools integration (System Generator, Vivado, Support Package...)
Please note that in HDL Coder R2014b, *both* Xilinx ISE and Vivado are supported as downstream tools. I understand that Yongfeng...

nästan 5 år ago | 0

Answered
Usage of Sum of Elements blockset from Altera DSP builder advanced blockset
I recommend that you check with Altera on this question because they will have more direct experience with the capabilities and ...

nästan 5 år ago | 0

Answered
Matlab Simulink with Altera Stratix III FPGA
Based on your explanation, I believe this would be supported by HDL Verifier, which supports FPGA-in-the-Loop with Stratix III b...

nästan 5 år ago | 0

Answered
2014b and HDL Coder
No -- as you observed, AXI-Stream is not supported with HDL Coder in R2014b.

nästan 5 år ago | 0

Answered
HDL verifier and zedboards
Architectural issues with Zynq have made it difficult to use the FIL feature of HDL Verifier with ZedBoard. In terms of other So...

nästan 5 år ago | 0

Answered
How to verify Altera IP core with Simulink?
MathWorks offers a number of ways to verify Altera IP cores with Simulink depending on use case. * If you have a reference m...

nästan 5 år ago | 1