Mitigation of Volt Sag by using DVR w/ PI and FL Controller

by wawa

POWER QUALITY PROBLEMS:

Circuit shared info:
The circuit is using a DLG fault (at phase B, C and Gnd) for the cause of volt sag.
There are 4 waveform for the simulated circuit which are the supply (Vabc), rms waveform for a better voltage sag analysis (Vabc_RMS), load voltage (V_load) and the injected voltage (V-inj) which is the DC supply used to mitigate the volt sag.

The author had simulated several PQ problems such as volt sag, notching and harmonics. The shared Simulink file are having pq problem of volt sag + notching. All of these 3 pq problems were mitigated by using dynamic voltage restorer (DVR). For the harmonics, the circuit have a parallel unbalanced load installed instead of DLG fault. The THD after the simulation is as below:

THD cause by unbalanced load = 25.96%
THD after installed DVR = 2.11%

#noted that the harmonics circuit will be shared later if many people requested. Otherwise, just follow the instruction above to simulate harmonics pq problem as it is very easy to construct.