The sigma-delta modulator based closed loop systems make high resolution, high SNR, low frequency systems. The sigma-delta analog to digital converter consists of the modulator followed by the decimation filter. In this project the design and FPGA implementation of decimation filter, which performs the action of filtering the shaped quantization noise and converting 1-bit data stream into 20 bit high-resolution output is reported.
The multi-stage decimation methodology is adapted, with the Cascaded Integrator Comb (CIC) filter followed by two FIR filters. The specifications of decimation filter are derived from the specifications of a third-order single bit sigma-delta modulator. Distributed arithmetic algorithm is used to design FIR filters. A software model is developed with the help of MatLab/simulink, and integrated with modulator model to analyze the response of the decimation section. The hardware model for the filter is developed using verilog HDL.
The design is implemented and tested using Actel APA 1000 FPGA. The test environment has the feature of taking external input as well as the internally stored bit stream in LUT .The system has got good linearity and design consumes a power of 40.4mw. An attenuation of 101db was measured at stopband.
INDRANIL SAAKI (2020). FIR Filter Based on DA Algorithm and FPGA Implementation (https://www.mathworks.com/matlabcentral/fileexchange/73461-fir-filter-based-on-da-algorithm-and-fpga-implementation), MATLAB Central File Exchange. Retrieved .