Space Vector Pulse Width Modulator For Three-Level Inverter

An SVPWM for 3-level inverters (T-Type or NPC) that can be directly deployed to DSPs and microcontrollers

The SVPWM is the technique that is most suitable to direct implementation on DSPs and microcontrollers since it has a ready fit with the PWM resources available on these devices. SVPWM for three-level inverters (whether T-Type or Neutral point clamped) is complex compared to the 2-level counterpart. The detailed development is hard to find anywhere in the available literature. In the attached two files, there given a pdf file that moves gradually along the steps required to find the ON-time control laws of the main six switches of these inverters (the other six are complementary and are automatically generated with dead-time insertion by the DSP). Also, a SIMULINK model is given to test the performance of the implemented algorithm. Application engineers who wish to use this algorithm should take care that no voltage unbalance correction mechanism is provided in this algorithm.
(The error fixed in version 1.0.1 is T1B dwell time was Tb+T0/2 but it should be Ts-T0/2. Now, this error is fixed in this version!
In this version, one of two possible balancing methods for the neutral point voltage is implemented without principal change in the main algorithm structure. The method uses redundant space vectors that can result in the same average poles voltages but have an opposite impact on the neutral point voltage to achieve the balancing. The modifications are easy to follow and the technical reference used is mentioned in the SVPWM block. The testing Simulink model compares the performance of the previous version with the current version. You can try the testing at different modulation indexes.