Best Practice Guide for SystemVerilog DPI Generation

Guide for learning how to efficiently generate SystemVerilog DPI-C components from MATLAB code for HDL simulators

Best Practice Guide for SystemVerilog DPI Component Generation

HDL Verifier™ facilitates the generation of SystemVerilog DPI and Universal Verification Methodology (UVM) testbench components directly from MATLAB® or Simulink®, bridging the gap between algorithm development and design verification. This guide is tailored to enhance your MATLAB workflow by providing recommended practices for preparing MATLAB designs for SystemVerilog DPI component generation.

In this guide, you will find comprehensive coverage of topics essential for evaluating MATLAB code compatibility with code generation, including:

• Getting started with code generation
• Converting scripts to functions
• Frame/stream modeling
• Working with vectors and matrices, including variable-sized vectors and matrices
• Using floating- and fixed-point data types
• Considerations for constrained randomization
• Generating UVM components