Is Stateflow not supported for Xilinx HDL code generation

Greetings - I am using a Virtex 5 ML506 board (since my VC707 is not supported) and am trying to do a FPGA in the loop simulation. I have a simple Stateflow diagram that I am trying to compile using HDL Coder. I've set the Target platform to Xilinx Virtex-5 ML506 Development board, the Synthesis tool as Xilinx ISE, etc. When I get to 2.3 in the HDL Workflow Advisor (Check Block Compatibility), it fails saying, "Error: This block is not supported for Xilinx Coregen mapping." This confuses me, as I thought Stateflow was supported. Any advice is welcome here ...

Answer 1

[Tim McBrayer]

From the error message it seems that you are trying to use Xilinx target library support. Is this intentional? This is controlled by the "Set Target Library (for floating-point synthesis support)" checkbox on Step 1.1 in the HDL Workflow Advisor.

Only certain blocks are supported by the Xilinx target library, and a Stateflow chart is not one of them. The way to correct this is to uncheck the Target Library setting when a Stateflow chart is part of the design.

[Wayne]

Hey there, appreciate the answer - you are right, that's exactly what was happening. The "Set Target Library" option was checked, and no it wasn't intentional ... thanks!