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HDL Coder black box inclusion of module with parameterised packed input

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Andrew Nicol
Andrew Nicol on 18 Sep 2020
Commented: Andrew Nicol on 2 Nov 2020
Hi all! I am trying to wrap some existing code of the form:
module foo #(
parameter int NInputs = 2
)(
input wire [NInputs-1:0][31:0] foo_in,
output logic [31:0] foo_out
);
When I generate code with the appropriate black box settings to set NInputs and drive foo_in with a vector of the coresponding size, HDL Coder is generating code such as the following:
foo #(.NInputs(2)
)
u_i_foo (.In1_0(In1), // uint32
.In1_1(In2), // uint32
.Out1(i_foo_out1) // uint32
);
As you can see, HDL Coder is creating inappropriate port names instead of connecting a packed vector.
How should I set up the model / HDL Coder to correctly to concatenate the subsystem input ports in such a way to get a packed N-element signal to pass to the black box? I considered just using the Bit Concat block and then using the Extract Bits block within the model of the black box, but that seems like it would get very brittle in terms of data type and dimension handling...

  1 Comment

John
John on 28 Sep 2020
I'm interested in this question as well. Anyone have any thoughts on this?

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Answers (1)

Kiran Kintali
Kiran Kintali on 1 Nov 2020
>> I considered just using the Bit Concat block and then using the Extract Bits block within the model of the black box, but that seems like it would get very brittle in terms of data type and dimension handling...
It looks like since you are not able to generate code in certain style for bit packing you are going towards a blackbox route.
can you share a sample model to support@mathworks.com?
>> I am trying to wrap some existing code of the form:
Regarding black box question please refer to this documentation
web(fullfile(docroot, 'hdlcoder/ug/black-box-implementation-for-subsystem-blocks.html'))
considering using the recent feature to wrap in a Doc block to make it self-sufficient.
web(fullfile(docroot, 'hdlcoder/ug/integrate-custom-hdl-code-using-docblock.html'))
>> As you can see, HDL Coder is creating inappropriate port names instead of connecting a packed vector. How should I set up the model / HDL Coder to correctly to concatenate the subsystem input ports in such a way to get a packed N-element signal to pass to the black box?
The reason you are not seeing the correct types for the ports is because you used "uint32 (2)". Based on limited description I am assuming you would need 2-d array of boolean/ufix1 type at the interface.

  1 Comment

Andrew Nicol
Andrew Nicol on 2 Nov 2020
Hi Kiran, the model I attached to my original post shows the problem quite well (obviously this is just a stripped down version of what I'm actually trying to do...). Let me know if that model is not clearly expressing what I'm trying to do.
Adding a DocBlock to the model doesn't seem to change the generation of the ports so maybe I'm missing something?
Regarding your last comment, I'm not sure I understand what you mean by using 2-d array of boolean/ufix1? For this test model, I need a packed array of two uint32s. I've tried using uint32 (2), uint32 [1x2], and uint32 [2x1] but I seem to get the same outcome for all configurations.

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