Regarding Xilinx GATEWAY IN Block in Simulink

Hi. I am facing a problem while using Xilinx blockset in Simulink. I am feeding an ECG input signal to the "GATEWAY IN" Block and at the output of the "GATEWAY IN" Block, my signal get distorted. I am attaching the input as well as output signal for your reference. I want my output signal same as input signal.

I feel this problem is due to sample period value selected in "GATEWAY IN" Block. This GATEWAY IN block does not take value less than 1 and due to it, the output is not the same as input. Kindly help.