Drawbacks in using Modele Reference in Simulink

Dear all,

I'm learning this nice feature of Simulink, namely the Model References. I think that way you can always keep your model clean, and you can test blocks separately before assembling them. However, I encountered several problems as I will discuss below. The model I'm simulating include a continuous-time first-order process modeled as a transfer function, and a discrete time PI controller. When embedding the process and the PI controller in subsystems, everything works fine, but if I use a model for the process and a model for the PI controller, and reference them in a new model several problems arise:

1. Algebraic loop (solved by using a time delay unit with inherited sampling time in the feedback channel of the complete scheme).

2. I get the "Warning: The model 'DT_PI' does not have continuous states, hence Simulink is using the solver 'VariableStepDiscrete' instead of solver 'ode45'. You can disable this diagnostic by explicitly specifying a discrete solver in the solver tab of the Configuration Parameters dialog, or by setting the 'Automatic solver parameter selection' diagnostic to 'none' in the Diagnostics tab of the Configuration Parameters dialog." -- I set "none" in the diagnostic tab in the Configuration Parameters Dialog in all the models, but I still have this warning.

3. Mismatching between the sampling times. "Warning: Inconsistent sample times. Sample time ([0, 1]) of signal driving input port 1 of 'ModelRefTL/Model1' differs from the expected sample time ([0.1, 0]) at this input port. Warning: Inconsistent sample times. Sample time ([0, 1]) of signal driving input port 2 of 'ModelRefTL/Model1' differs from the expected sample time ([0.1, 0]) at this input port. Warning: Inconsistent sample times. Sample time ([0.1, 0]) of signal driving input port 1 of 'ModelRefTL/Model' differs from the expected sample time ([0, 0]) at this input port." -- How can I accommodate these sampling times mismatches?

4. "When a unit delay block inherits continuous sample time, its behavior is the same as the memory block. Unit delay block's time delay will not be fixed and could change with each time step. This might be unexpected behavior. Normally, a unit delay block uses discrete sample time. You can disable this diagnostic by setting the 'Discrete used as continuous' diagnostic to 'none' in the Sample Time group on the Diagnostics pane of the Configuration Parameters dialog box." -- In-fact I used this unit time delay with inherited sampling time just to avoid using memory blocks and to cancel the algebraic loop. However, even if do as suggested in the Diagnostic Dialog, I still experience the warning in the command line.

How can I solve those problems? The Matlab version is the 2009b.

Thanks,

Ubaldo

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Answer 1

[Michael]

1. Yes, it is possible when turning a virtual subsystem into a referenced model, you may end up algebraic loops. There are two possible solutions:

   a. Turn on the parameter "Minimize algebraic loops" on the Model Referencing page of the configuration set of the referenced model. See the documentation here:

http://www.mathworks.com/help/toolbox/simulink/gui/bq7cyf9-1.html

   b. Try to make sure that blocks with states are connected to the root inputs of the referenced model.

2. Setting the Automatic solver parameter diagnostic parameter to None should work, I'm not sure why it's not working for you.

3. The referenced model is compiled independently from the parent model. So you need to explicitly set attributes on the root inports of the referenced model, for example you should set the sample time on the root inports to whatever is driving that inport.

4. Make sure you are changing the diagnostic in the model that is using the Unit Delay. Why don't you want to use the Memory block?

Answer 2

[Ubaldo Tiberi]

Thanks for the answer Michael, and sorry for the late reply.

1a. OK

1b. Which blocks with states? You mean the blocks with states of the referenced or the blocks with states of the main model must be connected to the root inports of the referenced model?

2. I don't why as well...

3. I think I solved the problem with the Rate Transition Blocks :)

4. I'm not using memory blocks because it implies to add 3 blocks and define new variables with the attributes (like scope etc), while my using the unit delay block it does everything automatically and it's needed only one block :-)

Ubaldo

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