Feedback Transition to a State in State Flow

So i want to state 1 the first time with the condition [Rising== 1 && n == 32] and then re enter it everytime from state 8 with the transition [Rising== 1 && n == 1]. Would this work?

When i implement this design using HDL coder and download it on the FPGA i don't see any output signal. I output my signals to simulink from state 8.

[Alain Kuchta]

Have you verified your design by simulating the Stateflow chart in Simulink? Is the output what you expect?

Do you want the condition for the transition from State_8 to State_1 to be [Rising== 1 && n == 1] or do you want to the action of the transition to be setting the value of Rising and n ?

[shauk]

Hallo I want the condition for the transition from State_8 to State_1 to be [Rising == 1 && n == 1]. But later i checked it on the simulink state flow chart and it works fine.

Answer 1

[Arunkumar M]

[Rising == 1 && n == 1] condition was used for entering State_8 as well as for exiting State_8. This makes State_8 to be active only for 1 task cycle. This could be the reason why you are not seeing any output from State_8.