How to use the dsp.HDLIFFT system object?

I am developing a symple OFDM modulator. I use QPSK symbols as input for the IFFT block (dsp.HDLIFFT). The problem is that my system is not working correctly, sometimes I receive the expected data and sometimes I don´t. I tested the QPSK alone and It works fine. But, when I put together the dsp.HDLIFFT wiht the QSPK modulador the system suffers the above problem.

Exampl of the problem:

A ===> [QPSK,IFFT] ====> B   (CORRECT) 1st Test
A ===> [QPSK,IFFT] ====> C   (INCORRECT) 2nd Test
A ===> [QPSK,IFFT] ====> D   (INCORRECT) 3rd Test
A ===> [QPSK,IFFT] ====> E   (INCORRECT) 4th Test
A ===> [QPSK,IFFT] ====> B   (CORRECT) 5th Test

The system works fine sometimes but as you can see above I receive wrong data most of the time.

My system object defination is:

 ifft128 = dsp.HDLIFFT('FFTLength',128,'ResetInputPort',true);

My code is something like this:

funciton tx = transmitter(rx)

UART_RX_funcion call
MAIN_FUNCTION call
UART_TX_function call

%%%%%%%%%%%%%%%%%%%%

[outputs] = main_fsm(inputs)

persistent a b c ifft128 ...

if isempty(a)
ifft128 = dsp.HDLIFFT('FFTLength',128,'ResetInputPort',true);
end

switch(state)

state1

state2

state3

end

[yOut,validOut] = step(ifft128,yIn,validIn,resetIn);

[Alireza]

Hi, Would you please provide your test bench and your code that I can try it? One minor thing in your main_fsm: You have a persistent called 'a'. It is never assigned but you look at it to create your fft object (if isempty(a) ...). since 'a' is not assigned, there will be a new ifft128 object each time you call this function. Is this intentional? Usually we write if isempty(ifft128) ...

Ali

[Pablo Medina]

Thanks for the reply. that persistent variables a b c are used in diferent states of my code. For example: a is a ram memory. I put them in the question just for reference.

In the other hand, my test bench is something like this:

data = int8([1 0 1 1 1 0 ...]) ==> 1X256 elements (256 bits because i want to have 128 QPSK symbols)

%UART RX  Each bit is represented by 16 ticks (1 tick is asserted after 651 clock cycles. Additionally, I used 1 Start Bit 8 data bits and 1 Stop bit. So, I use 320 bits in orden to send 256 data bits) 320*16*651 = 5120*651.

for i=1:5120*651    
    rx = data(j);
    if rem(i,10432)==0
        j = j + 1;
    end
    tx = transmitter(rx); 
end

%QPSK PROCESSING
for i=1:256    
    tx = transmitter(rx); 
end

%IFFT PROCESSING
for i=1:128    
    tx = transmitter(rx); 
end
%LATENCY OF IFFT
for i=1:196   
    tx = transmitter(rx); 
end

%UART TX (I used 14 bits representation for each OFDM symbol(128) and separeted th real and imaginary parts so, 14*128*2 = 3840)
for i=1:61440*651 
    tx = transmitter(rx); 
end

[Alireza]

Hi, To be able to reproduce the mismatch that you mentioned on your first post, I need the whole test bench. I couldn't reproduce the result with the code that you provided.

[Pablo Medina]

This is exactly my test bench, the data vector is a random binary sequence of bits (1s and 0s)

[Pablo Medina]

Everythin in the simulation works fine. But, when you implement the design you will not get the same results as the simulation. Sometimes you will receive correct data and sometimes you won´t.

[Alireza]

What do you mean by "implement"? HDL code generation and running in hardware?

[Pablo Medina]

I mean running the VHDL code generated by HDL Coder in an FPGA (Virtex 5)

[Alireza]

If it passes the RTL simulation (running HDL simulator), then the problem might be timing. You need to check if your design meet the timing is Xilinx.

[Pablo Medina]

Thans for the reply.

I have solved the problem eliminating some warnigns. But, I generate another VHDL Files with a diferent constants(same code just different phase vector), and the problem returned. My project has no timming constrains. Any other idea?

[Alireza]

You need to have a timing constraint when you synthesize, and make sure that the design meet the timing. Check the clock frequency of your design and create a timing constraint based on the clock frequency. After the synthesis and place and route, check if the design meet the timing.

[Pablo Medina]

Thanks for the answer I still looking forwar this timming contraint.