Ragarding the custom IP core generation using xilinx system generator

Hi there,

I have designed an up counter (counts from 0 to 10) using the system generator design flow. I exported the design as IP catalog and integrated the processor with the core and developed a software application to display the counter values.

But when i display the count values, the outputs are random values from 0 to 10. I am not able to figure out what's going wrong? Can anyone please help on this?

Thanks in advance..

(i have attached images below for better understanding)

regards shashi