Xilinx System Generator and HDL Workflow Advisor

I use Xilinx Blockset/Basic Elements/Black Box to integrate my hand-writing VHDL code under my "Top" subsystem block, and then I want to use HDL Workflow Advisor to generate my FPGA block. I got the error message.

Error reported by S-function 'sysgen' in 'blackbox_fpga/Top/Black Box': An internal error occurred in the Xilinx Blockset Library.

Thanks in advance for any help.

Answer 1

[Kaustubha Govind]

As far as I know, you need to use Xilinx System Generator to generate code from their blocks. They are not supported directly with Simulink HDL Coder. Refer to Xilinx documentation or support forums for information about using System Generator.

Answer 2

[Tim McBrayer]

I think you are using the wrong block to import your own black box code. As Kaustubha stated, the block you have chosen is specific to Xilinx System Generator and works only with that tool. To bring your custom code into Simulink HDL Coder, you can use a normal Simulink subsystem. Set its HDL Implementation Architecture to 'BlackBox' via the right-click context menu:

1. Right-click on the subsystem.
2. Choose 'HDL Code -> HDL Block Properties...".
3. For the Implementation Architecture, choose "BlackBox".
4. Set the parameters of the Black Box to match your code.
5. Click 'OK' when done.