Why do I get the error: " FIL cosimulation failed: the output does not match the expeced result" when I run FPGA-in-the-Loop Test?

3 views (last 30 days)
Hi, iI m trying to run the fpga in the loop test inside HDL coder. The HDL code was generated by a script in matlab (I didn't use a model in Simulink). I selected the board Xilinx Virtex Ultrascale VCU118 and the connection is JTAG ( my board has an onboard Digilent USB-JTAG module) . Then I added Vivado tool to MATLAB search path. When I tried to validate FPGA board, I obtain this error: "FIL cosimulation failed: the output does not match the expeced result ".
How can I fix it? Thank you.

Sign in to comment.

Answers (1)

Kiran Kintali
Kiran Kintali on 7 Sep 2022
If the HDL Code you are running is run with is generated from HDL Coder and is not matching the MATLAB or Simulink testbench then this is not an expected message. You can contact technical support with reproduction steps.


Find more on HDL Code Generation and Deployment in Help Center and File Exchange

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!