Frame To Samples
Convert frame-based data to sample stream
Wireless HDL Toolbox / I/O Interfaces
The Frame To Samples block flattens frame-based input into a stream of samples. The block also returns a stream of corresponding control signals that indicate sample validity and the boundaries of the frame. You can configure idle cycles inserted between samples or between frames, and how many values represent each sample. See Streaming Sample Interface for details of the streaming format.
Use this block to generate input for a subsystem targeted for HDL code generation. This block does not support HDL code generation.
frame — Frame of input samples
Frame of input samples, specified as a column vector. All samples in the vector are considered valid. Each frame must be the same size.
sample — Output sample stream
scalar | vector
Output sample stream, returned Output size values at a time. The output stream includes idle samples as specified by Idle cycles between samples and Idle cycles between frames. Each output sample has a corresponding set of control signals on the ctrl port.
ctrl — Control signals accompanying sample stream
Control signals accompanying the sample stream, returned as a
bus. The bus includes the
valid control signals, which indicate the boundaries of the frame
and the validity of the samples.
start— Indicates the start of the output frame
end— Indicates the end of the output frame
valid— Indicates that the data on the output data port is valid
For more details, see Sample Control Bus.
Idle cycles between samples — Number of idle cycles to insert after each sample
0 (default) | integer
Number of idle cycles to insert after each sample, specified as a scalar
integer. The block returns a vector of Output size
zeros for each idle cycle and sets all control signals to 0
Idle cycles between frames — Number of idle cycles to insert at the end of each frame
0 (default) | integer
Number of idle cycles to insert at the end of each frame, specified as a
scalar integer. The block returns a vector of Output
size zeros for each idle cycle and sets all control signals
to 0 (
Output size — Number of values representing each sample
1 (default) | positive integer
Number of values representing each sample, specified as a positive integer
scalar. The block outputs a vector of Output size
values. Each vector has one corresponding set of control signals. For
example, you can use this parameter to serialize turbo-encoded samples. In
the LTE standard, the turbo code rate is 1/3, so each sample is represented
by one systematic value and two parity values: S_n,
P1_n, and P2_n. In this case, set
Output size to
Compose output from interleaved input samples — Order of output samples relative to input order
off (default) | on
Order of output samples relative to input order, when more than one value
represents each sample. For example, for 1/3 turbo-encoded samples, the
input frame can be ordered
[S_1 P1_1 P2_1 S_2 P1_2 P2_2]
[S_1 S_2 P1_1 P1_2 P2_1 P2_2]. In the first case, the
output is two vectors,
[S_1 P1_1 P2_1] and
P1_2 P2_2]. To achieve the same output in the second case,
select Compose output from interleaved input
This parameter applies when Output size is greater than one.
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
This block supports C/C++ code generation for Simulink® accelerator and rapid accelerator modes and for DPI component generation.
Introduced in R2017b