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Video Capture (software interface)

Capture video to ARM processor on a Zynq-based video system that has an HDMI FMC card

  • Library:
  • Vision HDL Toolbox Support Package for Xilinx Zynq-Based Hardware

  • Video Capture (software interface) block

Description

The Video Capture (software interface) block provides a video capture and control interface to the FPGA reference design included with this support package. Use this block in a software model to design and deploy generated ARM® code for image processing on a Zynq® device. You can create a model for software targeting using the default FPGA design loaded at setup. You can also customize the FPGA logic and use targeted software to interface with your FPGA design.

To capture video to the ARM processor on a Zynq-based board that has a MIPI® FMC card, use the Video Capture MIPI block.

The HDL Workflow Advisor generates a software interface model that contains the Video Capture (software interface) block. The default parameter settings of the generated block match the settings of the Video Capture block in your original model. You can change the input video resolution, switch between HDMI input or an on-chip test pattern generator, and enable an optional bypass of the user logic section of the FPGA. When you change a parameter, the block writes an AXI-Lite register on the board.

When you use this block in a model deployed with the default FPGA image, you can change the video format that is imported to the ARM processor.

The FPGA user logic section is the IP core that you generate from your design using HDL Workflow Advisor. If you enable the bypass of the FPGA user logic, the HDMI output is the same as the HDMI input. Points A and B in the diagram show the options for capturing video into the ARM processor.

The video data is a pixel stream on the FPGA. When you capture the video to the ARM processor, the stream is converted to frame-based video.

FPGA design diagram showing the HDMI video input is converted to the specified format and routed through the FPGA user logic.

Required Products

To use the Video Capture (software interface) block in either the generated model or a model you create yourself, these products are required:

  • Embedded Coder®

  • Embedded Coder Support Package for Xilinx® Zynq Platform

Ports

Output

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The block returns one matrix for each color component of the input video. The dimensions of the Y matrix match the frame size. The dimensions of the Cb and Cr matrices are height-by-width/2 because the 4:2:2 format alternates Cb and Cr values for each pixel in the frame.

Dependencies

To enable these ports, set Pixel format to YCbCr 4:2:2.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

The block returns one matrix for each color component of the input video. The dimensions of each matrix match the frame size.

Dependencies

To enable these ports, set Pixel format to RGB and Image signal to Separate color signals.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

The block returns a 3-by-height-by-width matrix, where height and width match the frame size.

Dependencies

To enable this port, set Pixel format to RGB and Image signal to One multidimensional signal.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

The block returns a matrix whose dimensions match the frame size.

Dependencies

To enable this port, set Pixel format to Y only.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

Parameters

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The video stream through the FPGA logic and ARM processor can start with input video from the HDMI port of the camera board or with generated video from the test pattern generator (TPG). This parameter is tunable.

  • HDMI input (default) — HDMI input port on the FMC-HDMI-CAM board. Set the Frame size parameter to match the resolution of your attached camera.

  • Test pattern generator — On-chip TPG.

    The TPG creates input frames at the requested resolution. The test pattern is a fixed color bar pattern. When you select the TPG, you do not need a camera or other HDMI source connected to the board. The FMC card is still required.

    Video test pattern captured when you set the Video source parameter to Test pattern generator.

Select from HD and SD TV resolutions and common computer frame sizes. If the resolution you select does not match the resolution of the HDMI input source, the block returns an error.

For most frame sizes, this parameter is informational. Frame size 576p supports only 50 fps. Most other frame sizes support only 60 fps, except for 720p and 1080p.

When you use frame sizes 720p or 1080p, you can select from the available frame rates.

The block sets the Simulink® sample time for the captured video frames to 1/Frame rate.

When you customize the FPGA user logic, this parameter is informational only. In the generated software interface model, this parameter displays the configuration you selected in the Video Capture block before you generated HDL code. When you use the default FPGA logic, you can select any pixel format.

  • RGB — Three 8 bit color components per pixel, which is 24 bits per pixel total. You can also select the color space conversion standard and whether the block returns a multidimensional signal or three separate color signals. For details, see the Use color space conversion specified by and Image signal parameters, respectively.

  • Y only — Grayscale. One 8 bit component per pixel. The block returns the frames on the Y output port.

  • YCbCr 4:2:2 (default) — Also known as YUYV. An 8 bit Y component and an interleaved 8 bit CbCr component. The effective pixel size is 16 bits. The block returns the component frames on the Y, Cb, and Cr output ports.

This parameter specifies the equation that is used to convert between RGB and YCbCr color spaces. For more information, see the Color Space Conversion (Computer Vision Toolbox) block.

When you customize the FPGA user logic, this parameter is informational only.

Dependencies

To enable this parameter, set Pixel format to RGB.

Select this parameter to bypass the user logic section of the FPGA and send the input video frames directly to the HDMI output. When you select this option, capture point A and B observe the same video data. This parameter is tunable.

You can import frames to the ARM processor from the input or output of the user logic section of the FPGA. This section of logic is a pass-through in the default FPGA image. The data path diagram in the Description section of this page shows the capture points A and B.

  • Input to FPGA user logic (A) — Capture frames after conversion and before the user logic section.

  • Output from FPGA user logic (B) — Capture frames after the user logic section and before conversion back to HDMI output.

  • No capture — No video data is passed to the ARM processor. You can still use the block to control the video options on the FPGA.

Specify the RGB output stream format as one of these values.

  • Separate color signals — The block returns separate height-by-width matrices for each color component. In this case, the block has R, G, and B output ports.

  • One multidimensional signal — The block returns a single 3-by-height-by-width matrix. In this case, the block has an Image output port.

Dependencies

To enable this parameter, set Pixel format to RGB.

The value of this parameter matches your target interface selection when you generated HDL code from your pixel-stream model, and is read-only.

  • Pixel-stream video — The FPGA user logic interface is implemented using the Vision HDL Toolbox™ custom pixel-streaming interface. The signal protocol for this interface matches the protocol that is simulated in the Simulink model. The default FPGA image uses this interface.

  • AXI4-stream video — The FPGA user logic interface is implemented using an AXI4-Stream Video interface. This standard interface enables you to integrate your custom algorithms with other vision processing IP blocks.

Version History

Introduced in R2016a