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Simulation Problems and Fixes

Model runs but receives no data from board

Problem

When you run the model in external mode, the simulation time advances, but the model receives no video data from the board.

Possible Solution

Check the Configuration Parameters of the model. On the Solver pane, clear Treat each discrete rate as separate task. For other model settings, see Step 3. Configure Model.

Possible Solution

Verify that the interface of the FPGA user logic running on the board matches the Streaming interface parameter setting of the Video Capture block. If your FPGA image uses the AXI4-Stream Video interface and you set this parameter to Pixel-stream video, the block does not capture any data to the model.

Model stops at T=0

Problem

When you run the model in external mode, the simulation stops at T=0.

Possible Solution

Check the Configuration Parameters of the model. On the Hardware Implementation pane, expand Target hardware resources and clear Run external mode in a background thread.

For other model settings, see Step 3. Configure Model.

Resolution of target for HDMI input did not match frame size as set in model

Problem

The resolution of the HDMI input source does not match the resolution captured with the Video Capture block. Your camera may not have been able to negotiate a supported resolution with the FMC-HDMI-CAM card. The camera may fall back to an alternate resolution if negotiation fails.

For example, when you are attempting to get HDMI input from an iPhone or iPad mini, you might see this error:

The resolution of the target for HDMI input did not match the frame 
size as set in the model. Update the target by changing the camera 
settings or the model by changing the mask parameters.
 Actual: 1280x720 Expected: 1920x1080
The system did not succeed in negotiating 1080p resolution. The phone falls back to 720p. 

Possible Solution

Match your settings for the camera source and the Video Capture block.

Unplug and reattach your camera to redo the negotiation.

Always use 1080p for an iPhone or iPad mini. If the device was connected and turned on when you powered on the board, the device falls back to 720p. If you run a simulation without changing anything, you get the message that the resolution does not match.

If you cannot get a particular camera to work, contact technical support.

Computed fixed step size X is Y times smaller than all discrete sample times in model

Problem

The ratio between the frame rate and the pixel rate is too large for the automatic Simulink® solver counters.

Possible Solution

Copy and paste the fixed step size, X, in the error message to the Fixed-step size (fundamental sample time) parameter in Configuration Parameters.

The sample time is pixelSampleTime = 1/(frameRate*totalVideoLines * totalPixelsPerLine), where totalVideoLines and totalPixelsPerLine are settings derived from the resolution on the Frame to Pixels block. These dimensions represent the total frame size including blanking intervals between active lines and frames. frameRate is automatically configured to match the Frame size parameter of the Video Capture block. Most resolutions use 60 fps.

The error message suggests using the variable step solver, but this solver is not supported for multirate models in the HDL Workflow Advisor.

Warning: HDL test bench generation for multirate models requires fixed step, discrete solver

Problem

The model is not configured to use a fixed-step solver. If the ratio between the frame rate and the pixel rate is too large for the automatic Simulink solver counters, you may need to customize the step size.

Possible Solution

In Configuration Parameters, select the Fixed-step and discrete solver options. Set the Fixed-step size (fundamental sample time) parameter to auto. Alternatively, set the step size to pixelSampleTime = 1/(frameRate*totalVideoLines * totalPixelsPerLine), where totalVideoLines and totalPixelsPerLine are settings derived from the resolution on the Frame to Pixels block. These dimensions represent the total frame size including blanking intervals between active lines and frames. frameRate is automatically configured to match the Frame size parameter of the Video Capture block. Most resolutions use 60 fps.

All sample times in your model must be integer multiple of fixed-step size

Problem

Your fixed-step size does not account for the blanking intervals added around the active frame by the Frame to Pixels block. The inactive pixels imitate the timing of a physical video system, and many streaming video processing algorithms rely on this space between active lines and frames.

Possible Solution

Set the Fixed-step size (fundamental sample time) parameter to auto. Alternatively, set the step size to pixelSampleTime = 1/(frameRate*totalVideoLines * totalPixelsPerLine), where totalVideoLines and totalPixelsPerLine are settings derived from the resolution on the Frame to Pixels block. These dimensions represent the total frame size including blanking intervals between active lines and frames. frameRate is automatically configured to match the Frame size parameter of the Video Capture block. Most resolutions use 60 fps.

Error(s) encountered while building "modelname": Failed to generate all binary outputs.

Problem

'/arm-xilinx-linux-gnueabi-gcc' is not recognized as an internal or external command, 
operable program or batch file. 

You have not set up the Xilinx®-ARM® cross-compiler tool path for Embedded Coder® Support Package for Xilinx Zynq® Platform.

Possible Solution

Run the manual setup steps in Setup for ARM Targeting.

Error evaluating 'StartFcn' callback of subsystem block (1)

Problem

Caused by:
Cannot establish an SSH connection to the board with device address "192.168.4.2".
Error executing command: FATAL ERROR: Network error: Connection timed out

Check the connection to your Zynq device.

If the device address is 10.10.10.1, you have not run the manual setup steps for Embedded Coder Support Package for Xilinx Zynq Platform.

Possible Solution

Run the manual setup steps in Setup for ARM Targeting.

Error evaluating 'StartFcn' callback of subsystem block (2)

Problem

Caused by: 
Error executing command "/mnt/visionzynq-tools/visionzynq-target-dev.elf --write --device=/dev/mwipcore_vht2vs --address=0x00 0x01".
This error message indicates that the FPGA image loaded on the board uses the Vision HDL Toolbox™ interface but the Video Capture block has the Streaming interface parameter set to AXI4-stream video.

Possible Solution

Use the Video Capture block from the visionzynqlib library. The library block has the Streaming interface parameter set to Pixel-stream video.

Alternatively, load an FPGA image to the board that has an AXI4-Stream Video interface on the FPGA user logic.

Video Viewer block shows only the first and last frames of the video

Problem

The Video Viewer block continues to show the first frame during simulation, and the time display at the bottom of the viewer does not match the current simulation time. The viewer then updates to show the final frame at the end of simulation.

Possible Solution

If the Drop Frames to Improve Performance parameter of the Video Viewer block is selected, the viewer can drop frames to improve simulation speed. To visualize all frames during simulation, on the Simulation tab of the Video Viewer block, clear the Drop Frames to Improve Performance parameter.

Not enough memory on target to process packet: EXT_SELECT_SIGNALS

Problem

If your model includes the Video Viewer block, external mode simulation with the default trigger duration settings runs out of memory while processing the video data frames.

Possible Solution

Reduce the duration of the external mode trigger to avoid buffering errors. In the Code menu, select External Mode Control Panel. Click the Signal & Triggering button. In the Trigger options section, set the Duration parameter to 1.