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Target FPGA on Zynq Hardware

Workflow diagram that highlights the 'Deploy to FPGA' step described on this page.

FPGA targeting starts when you generate HDL code to represent a subsystem in your design. To support HDL code generation, you must design the subsystem with hardware implementation in mind. Hardware vision processing applications use a pixel-streaming interface rather than frame-based video. From the generated code, the software creates a custom image for the FPGA fabric. This custom bitstream is then downloaded to the FPGA on the development board. This procedure enables you to implement your custom algorithm on Zynq® development hardware, providing these advantages.

  • By moving part or all of your algorithm to the hardware, you speed up the host processing.

  • You can use FPGA targeting for prototyping designs on real hardware.

In addition to generating and deploying the FPGA image, the FPGA targeting workflow generates two Simulink® models: a hardware interface model and a software interface model. The tool also creates two libraries that contain the interface blocks used in these two models. If you do not have the Embedded Coder® product installed, the targeting tool cannot create the software interface model and its associated library.

The hardware interface model controls the reference design from the Simulink model without Embedded Coder. The software interface model supports software targeting to the ARM® processor on the Zynq device by using Embedded Coder.

This page describes the workflow for capturing and processing video from an HDMI FMC card or a MIPI® FMC card. To target the deep learning reference design, see Deploy and Verify YOLO v2 Vehicle Detector on FPGA.

Required Products

To generate the hardware interface model, you must have these products.

  • HDL Coder™

  • HDL Coder Support Package for Xilinx® Zynq Platform

To generate the software interface model, you must have these products.

  • Embedded Coder

  • Embedded Coder Support Package for Xilinx Zynq Platform

Step 1: Open Model

Open the model that contains the Video Capture or Video Capture MIPI block and the subsystem you are targeting for your Zynq device.

Step 2: Set Tool Path

In preparation for targeting, set up the Xilinx tool chain by calling the hdlsetuptoolpath (HDL Coder) function. For example, at the MATLAB® command prompt, enter this command and replace C:\Vivado\2020.2\bin\vivado.bat with the correct path for your Vivado® installation.

hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','C:\Vivado\2020.2\bin\vivado.bat');

Step 3: Create Zynq Files Using Workflow Advisor

  1. Make sure that your vision hardware is connected to and communicating with the host computer.

    If you are unsure whether your vision hardware is connected correctly and whether it is communicating with the host computer, you can check the connection by running the Getting Started with Vision Zynq Hardware example, or the Getting Started with MIPI Sensor example.

  2. Start the HDL Workflow Advisor by right-clicking the subsystem that contains the algorithm and selecting HDL Code > HDL Workflow Advisor.

  3. In the left pane, click 1. Set Target.

  4. Click 1.1 Set Target Device and Synthesis Tool, and then set these options.

    • Set Target workflow to IP Core Generation.

    • Set Target platform to your vision hardware.

      For an HDMI FMC Card, select one of these options.

      • ZCU106 FMC-HDMI-CAM

      • ZCU102 FMC-HDMI-CAM

      • PicoZed FMC-HDMI-CAM

      • ZC702 FMC-HDMI-CAM

      • ZC706 FMC-HDMI-CAM

      • ZedBoard FMC-HDMI-CAM

      For a MIPI FMC card, select ZCU106 IMX274MIPI-FMC.

    • Set Project folder to a valid path for the location of your project folder.

    All other fields are populated automatically. This image shows example parameter settings for Step 1.1.

  5. Click 1.2 Set Target Reference Design, and then set these options.

    • Reference design

      • HDMI FMC Card

        For a HDMI FMC card, select a reference design according to the pixel format that the FPGA user logic expects, and the interface that you want the FPGA user logic to use. By default, the tool generates FPGA user logic with the Vision HDL Toolbox™ custom pixel-streaming interface. Alternatively, you can select an AXI4-Stream Video interface. This interface is useful if you plan to integrate your generated FPGA logic into a larger design that uses the standard AXI4-Stream Video interface.

        To use the Vision HDL Toolbox custom pixel-streaming interface, set the Reference design parameter to RGB, Y only, or YCbCr 4:2:2.

        To use the AXI4-Stream Video interface, set the Reference design parameter to RGB AXI4-Stream Video Interface, Y only AXI4-Stream Video Interface, or YCbCr 4:2:2 AXI4-Stream Video Interface.

        • RGB: Three 8-bit color components per pixel. This format represents each pixel by 24 bits in total.

        • Y only: One 8-bit component per pixel. This format is similar to intensity, but the pixel values are in the range [16, 235].

        • YCbCr 4:2:2: An 8-bit Y component and an interleaved 8-bit CbCr component. This format represents each pixel by 16 bits and is also known as YUYV format. The data range for Y is [16, 235], and the range for Cb and Cr is [16, 240].

      • MIPI FMC Card

        To use a MIPI FMC card, set the Reference design parameter to MIPI Receive path. This reference design implements the AXI4-Stream Video interface for RGB video data. Each pixel has three 8-bit color components. This format represents each pixel by 24 bits in total.

    • Source Video Resolution

      Optionally, select the resolution of your input video. If your design uses multipixel streaming, the dimensions of the video resolution must all be multiples of the number of pixels per cycle.

      Note

      The resolution of the output video stream from the FPGA user logic must match the resolution of the input video. You cannot change the dimensions of the video inside the FPGA user logic.

      When you use an HDMI FMC card, the tool calculates the necessary clock frequency to support the resolution you select, and adds a synthesis constraint. By default, the design is synthesized using a clock constraint of 148.5 MHz on the HDMI pixel clock. This rate supports a maximum resolution of 1080p HDTV at 60 frames per second. Because the HDL Workflow Advisor overwrites the DUT Synthesis Frequency value with a value calculated based on the selected resolution, do not modify the DUT Synthesis Frequency parameter directly.

      When you use the MIPI FMC card and a scalar pixel stream, the tool specifies a synthesis target clock frequency of 300 MHz. When you use the MIPI FMC card and a 2-pixel-per-clock stream, the tool specifies a synthesis target clock frequency of 150 MHz.

      After Step 4.3, check the synthesis logs for your design to verify that the synthesis achieved the requested clock frequency.

    • Number of Pixels Per Clock

      If your design uses multipixel streaming, set this reference design parameter to match the setting in the Frame To Pixels block in your model.

      • The HDMI card reference design supports scalar streams and 2-, 4-, or 8-pixels-per-clock streams.

      • You cannot use multipixel streaming with an HDMI design that uses the AXI4-Stream Video interface.

      • The MIPI card reference design supports scalar streams and 2-pixels-per-clock streams.

    This image shows example parameter values for Step 1.2.

  6. Click 1.3 Set Target Interface, and then map the ports of your subsystem to available hardware interfaces provided by the reference design.

    • If you have an HDMI FMC card, and you use the default Vision HDL Toolbox pixel-streaming interface, map the ctrl bus ports to the custom Pixel Control Bus Input and Pixel Control Bus Output interfaces. The signals are flattened in the generated HDL code.

    • If you have a MIPI FMC card, or you have an HDMI FMC card and use the AXI4-Stream Video interface, map the input color component and CtrlIn bus port to the AXI4-Stream Video Slave interface, and the output color component and CtrlOut bus ports to the AXI4-Stream Video Master interface.

    • If your design uses external memory, map the related ports to either frame buffer or AXI manager interfaces. For a frame buffer, map the write interface to Frame Buffer Master and the read interface to Frame Buffer Slave. For random access, map the write interface ports to AXI4 Master Write and the read interface ports to AXI4 Master Read. For more detail, see Model Frame Buffer Interface and Model AXI Manager Interface.

    • Set Processor/FPGA synchronization to Free running (default). Coprocessing mode is not supported.

    • If your design uses multipixel streaming, each pixel port is automatically set to a bit width that accommodates the number of pixels. For example, for a multipixel design with 4 pixels per cycle, and pixel values of data type uint8, Step 1.3 shows a port width of 32 bits. For an example, see MultiPixel-MultiComponent Streaming with Zynq-Based Hardware.

    This image shows example parameter settings for Step 1.3, for an HDMI FMC card that uses the default Vision HDL Toolbox pixel-streaming interface.

    This image shows example parameter settings for Step 1.3, for an HDMI FMC card with a YCbCr AXI4-Stream Video interface.

  7. Click 2. Prepare Model for HDL Code Generation. Run all tasks through 2.4. If any task fails or warns, correct the issue. You cannot continue to the next step until you resolve all reported failures.

    You do not need to modify settings in Step 3. If you are already familiar with preparation and HDL code generation phases, you can right-click Step 4.1 and select Run to selected task.

    Note

    In Step 3.1.2, leave the Oversampling factor parameter set to 1.

  8. In Step 4.2, click Run This Task. The HDL Workflow Advisor generates these models and libraries:

    • A hardware interface model and a library that contains the interface blocks from this model.

    • A software interface model and a library that contains the interface blocks from this model, if the Embedded Coder Support Package for Xilinx Zynq Platform support package is installed. You also must have run the manual setup steps in Setup for ARM Targeting.

    For more information about these models and libraries, see Models Generated from FPGA Targeting.

  9. In Step 4.3, the HDL Workflow Advisor generates a programming file for the FPGA. To execute this step in an external shell so that you can continue to use MATLAB while the FPGA builds, keep the selection Run build process externally. The build can take about 20 minutes or more to complete. When the build is finished, a message in the command window notifies you that you can close the window.

    Note

    After the HDL Workflow Advisor completes basic project checks, it shows this step as completed while the FPGA is still being built. Wait until the external shell shows a successful image build before moving on to the next step.

  10. In Step 4.4, to download the completed FPGA image to the target hardware, click Run This Task. All prior tasks must have a result of Passed or Warning. This step renames the generated bitstream file and moves it to the hdl_prj/vivado_ip_prj/sdcard folder.

    You can manually download any bitstream file from this directory to the target hardware by running these commands at the MATLAB command prompt. Replace BITSTREAM_NAME with the name of your file. The device tree files ship with the software and the file names indicate the board and the interface used by the FPGA user logic. Specify the device tree configuration file that matches your board and the interface you selected for your FPGA user logic. For example, the device tree file shown in this example is for use with the ZCU102 board and an HDMI FMC card when the FPGA user logic has an AXI4-Stream Video interface.

    vz = visionzynq();
    downloadImage(vz,'FPGAImage','BITSTREAM_NAME.bit', ...
    'DeviceTree','visionzynq-zcu102-hdmicam-axi-video.dtb'); 
    After a new bitstream is loaded, the software reboots the board.

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