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Design Frame-Based Algorithms

Workflow Overview

Workflow diagram that highlights the 'Develop frame-based algorithm' step described on this page.

With this support package, you can import live video frames from the Zynq® device into a Simulink® model. You can then design and verify frame-based algorithms using Computer Vision Toolbox™ blocks. The model templates for frame-based algorithms help you get started. To open a template, see Create Model Using Simulink Templates.

To model frame-based designs with video captured from a MIPI® FMC card, start with the "RGB for Frame-Based Algorithms with Zynq" template, and replace the Video Capture block with the Video Capture MIPI block. The MIPI card reference design only supports capture in RGB format.

Y-only frame-based Simulink template model.

Each template has three shaded areas:

  • Source — Contains the video data sources for your model. The Video Capture block provides live camera data or a test pattern from the hardware device. Alternatively, you can select a data file input.

  • Algorithm — Contains the subsystem where you design your algorithms. This subsystem can include ports for physical board signals. It can also include ports connected to AXI-Lite registers, which you can control from the ARM® processor.

  • Display — Contains the display and evaluation of the results of the video processing algorithm.

To capture video from the hardware board with a HDMI FMC card, the support package implements the following design on the FPGA. Without any FPGA user logic added, the video captured from both points is identical.

FPGA reference design for HDMI FMC card.

To capture video from the hardware board with a MIPI FMC card, the support package implements the following design on the FPGA. Without any FPGA user logic added, the video captured to Simulink is the MIPI video input after demosaic and gamma correction.

FPGA reference design for MIPI FMC card.

After you are satisfied with the results of the video processing in Simulink, you can convert all or part of the algorithm to a pixel-streaming design targeted to the FPGA. See Design Pixel-Streaming Algorithms for Hardware Targeting.

See Also

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