Read AXI4-Stream Data using IIO
Embedded Coder Support Package for Xilinx Zynq Platform
This block reads data from the direct-memory-access (DMA) buffer of the specified AXI4-Stream IP core device by using the Industrial I/O (IIO) library drivers. The AXI4-Stream IIO Read block enables you to achieve a low-latency, high-throughput data transmission between your model deployed on the processor and the IP core on the FPGA. This diagram shows the control signals and path of the data before it reaches this block..
Data— Data frame from DMA buffer
This port outputs the N-by-1 vector received from the DMA buffer transfer. Use the Frame size parameter to determine the number of samples read for each DMA transfer. This port is unnamed until the Valid port is enabled.
Valid— Status of stream read from IP core
This port outputs a validation flag indicating a successful read of the data from
the IP core, where
1 indicates a successful read.
To enable this port, set Data timeout (seconds) to a finite value.
IIO device name— File name of IP core device
mwipcore0:s2mm0(default) | character array
Enter the name and channel of the IP core on the FPGA as a colon separated list. If
you are using HDL Coder™ to generate the IP core, HDL Coder maps the IP core to
mwipcore0 and uses channel
s2mm0. For more information on getting IIO device names and
channels, see Tips.
Frame size— Size of data vector to be read from IP core
1024(default) | positive integer
Enter the size of the data vector to be read from the IP core device.
Data type— Data type of IP core
Select the data type used by the IP core.
Sample time— Sample time in seconds
0.1(default) | positive scalar
The signal data output by the AXI4-Stream IIO Read blocks polls from the DMA buffer using the AXI4-Stream protocol. The Sample time or base-rate of the subsystem specifies the polling rate of the DMA buffer.
Data timeout (seconds)— Timeout for DMA stream read
Inf(default) | positive scalar
Specify the maximum time out delay for the DMA stream read.
To get a list of available IIO device names and channels, open a terminal into the Xilinx® Zynq® hardware board, and execute this command.