This workflow enables algorithm and system designers to generate an HDL IP core and integrate it into a fixed reference design for rapid prototyping. Create an SoC model based on the selected reference design for the supported Xilinx® RFSoC devices by using the SoC Model Creator tool. Use the created model as a template to design and simulate your FPGA algorithm and processor algorithm. Then, generate a bitstream and host I/O model, build a software application, and program the board by using the SoC Builder tool.
Customize and design an SoC model by using the SoC Model Creator tool.
Generate an RFSoC system by using RFSoC support for a fixed reference design workflow.
Choose between the SoC Builder tool and the
socExportReferenceDesign function for deploying your design
on an SoC device.
|AXI4-Stream IIO Write (HOST)||Write arrays to DDR memory buffer of IP core device from simulation model|
|AXI4-Stream IIO Read (HOST)||Read DDR memory buffer from IP core device into simulation model|
|AXI4-Register IIO Read (HOST)||Read memory-mapped registers into simulation model|
|AXI4-Register IIO Write (HOST)||Write data to memory-mapped registers from a simulation model|
|ADC To Vector||Convert concatenated 16-bit ADC input samples to vector outputs|
|Vector To DAC||Convert vector inputs to concatenated 16-bit DAC output samples|
|SoC Model Creator||Create SoC model based on selected RFSoC reference design|
|Configure the RF Data Converter on the RFSoC device from MATLAB|