The IP core generation workflow enables system designers to generate a reusable HDL IP core for supported Xilinx® RFSoC devices. SoC Blockset™ RFSoC reference designs enable you to use the IP core generation workflow when your system includes an external memory and I/O.
Use the SoC Template Builder tool generate a template model based on the selected reference design and a host I/O model for data streaming and AXI memory map access with Simulink®. Customize the model template to include your algorithm. Then, use the HDL Workflow Advisor (requires HDL Coder™) to generate a bitstream and program the board.
This workflow customizes and designs an RFSoC model using the SoC Template Builder tool.
This workflow generates an RFSoC system using the IP core generation workflow.
Set up the clock between the RFSoC and the DUT and set sampling rates.
|AXI4-Stream IIO Write (HOST)||Write arrays to DDR memory buffer of IP core device from simulation model|
|AXI4-Stream IIO Read (HOST)||Read DDR memory buffer from IP core device into simulation model|
|AXI4-Register IIO Read (HOST)||Read memory-mapped registers into simulation model|
|AXI4-Register IIO Write (HOST)||Write data to memory-mapped registers from a simulation model|
|ADC To Vector||Convert concatenated 16-bit ADC input samples to vector outputs|
|Vector To DAC||Convert vector inputs to concatenated 16-bit DAC output samples|
|SoC Template Builder||Generate template model based on selected RFSoC reference design|
|Configure the RF Data Converter on the RFSoC device from MATLAB|