To program the FPGA and run your algorithm on the hardware, HDL Coder™ can generate an IP core, and deploy it to the Xilinx® FPGA boards. You can also program the FPGA board by using the FPGA Turnkey workflow, which generates HDL code for your algorithm and the FPGA top level wrapper and then deploys your design to the board.
IP Core Generation
- IP Core Generation Workflow for Xilinx FPGA Boards
Learn how to use the IP Core Generation workflow with standalone FPGA devices and embed the IP core into the reference design.
- Default System Reference Design
Learn about the default system reference design and using the reference design.
- Program Standalone Xilinx FPGA Development Board from Simulink
This example shows how to target a Xilinx FPGA development board for synthesis using the FPGA Turnkey workflow.
- Program Standalone Xilinx FPGA Development Board from MATLAB
FPGA Turnkey workflow for deployment to standalone FPGA hardware.