This example shows you how to use Embedded Coder® Support Package for ARM Cortex-M™ Processors for code verification and validation using PIL.
In this example you will learn how to configure a Simulink model to run Processor-In-the-Loop (PIL) simulations. In a PIL simulation, the generated code runs on a QEMU ARM Cortex-M3 emulator. The results of the PIL simulation are transferred to Simulink to verify the numerical equivalence of the simulation and the code generation results. The PIL verification process is a crucial part of the design cycle to ensure that the behavior of the deployment code matches the design.
This example introduces the Simulink code generation and verification workflow by showing you how to:
Configure a Simulink model to run PIL simulations on the ARM Cortex-M3 (QEMU) emulator target
We recommend completing the Getting Started with Embedded Coder Support Package for ARM Cortex-M Processors example.
This example shows how to use a PIL block for subsystem code verification. With this approach:
You can verify the code generated for a subsystem
You must provide a test harness model to supply a test vector or stimulus inputs
You must swap your original subsystem with a generated PIL block; you should be careful to avoid saving your model in this state as you would lose your original subsystem
1. Open the PIL Block model. This model is configured for the ARM Cortex-M3 (QEMU) target. The objective here is to create a PIL block out of the Controller subsystem that you will run on the QEMU ARM Cortex-M3 emulator.
2. Open the Modeling tab and press CTRL+E to open Configuration Parameters dialog box. Go to Code Generation > Verification > Create block, and select PIL.
Alternatively you can enable PIL from MATLAB command window through the following command set_param('arm_cortex_m_pil_block','CreateSILPILBlock','PIL')
3. Create a PIL block for the Controller subsystem:
a. Right click on Controller block in PIL, and go to C/C++ Code and select Deploy this subsystem to Hardware.
b. Select Build from Build code for subsystem:Controller dialog box.
4. Run the PIL simulation:
a. Copy and place the PIL Cortex-M3 Controller block in the PIL block.
b. Click the Run icon (or press Ctrl+T) to simulate the model.
5. Once you start the simulation, a QEMU session running the PIL block is launched. You can switch between the original and PIL block subsystems by double clicking on the Manual Switch block. Double click on the Numerical Differences block to see the difference between the simulated Controller subsystem and the PIL block running on the QEMU emulator.
This example shows how to verify the generated code for a referenced model by running a PIL simulation. With this approach:
You can verify code generated for referenced models
You must provide a test harness model to provide a test vector or stimulus inputs
You can easily switch a Model block between normal and PIL simulation mode
1. Open the Model Block PIL model. This model is configured for the ARM Cortex-M3 (QEMU) target. The model contains two Model blocks that both point to the same referenced model. You will configure one Model block to run in PIL mode while the other one will be set to normal mode.
2. Configure and run the CounterA Model block in PIL mode:
a. Right click on CounterA block and select Block Parameters (ModelReference)
b. Select Simulation mode > Processor-in-the-loop(PIL) and click OK
3. When the model starts running, Scope1 displays the PIL simulation output running on the QEMU emulator while Scope2 shows the normal mode simulation output.
This example shows how to verify the generated code for a model by running a PIL simulation. With this approach:
You can verify code generated for a top model
You must configure the model to load test vectors or stimulus inputs from the MATLAB workspace
You can easily switch the entire model between normal and PIL simulation mode
1. Open the Top Model PIL model. This model is configured for the ARM Cortex-M3 (QEMU) target.
2. Run the top model PIL simulation:
a. Open the Apps tab and select SIL/PIL Manager.
b. On the SIL/PIL tab, select SIL/PIL Mode > Processor-in-the-loop(PIL) option and click Run Verification.
3. When the PIL simulation terminates, a logsOut variable is created in the base workspace. The logsOut data contains PIL simulation results. You can access the logged data for signals count_a and count_b using the following commands:
count_a = get(logsOut,'count_a');
count_b = get(logsOut,'count_b');
This example introduced code verification workflow using PIL simulation.