Hardware-Software Co-Design Basics

Learn about the hardware-software co-design workflow and how to use the Workflow Advisor to run the algorithm on the SoC platform

You can use the hardware-software co-design workflow to partition your design to run on SoC platforms. With the HDL Workflow Advisor, you can use the IP Core Generation workflow to generate an HDL IP core that runs on the FPGA on board the SoC. Using Embedded Coder®, you can generate and build the embedded software, and run it on the ARM® processor.

Topics

Hardware-Software Co-Design Workflow for SoC Platforms (HDL Coder)

High-level workflow steps for targeting an SoC platform

Getting Started with the HDL Workflow Advisor (HDL Coder)

Learn the basics of the HDL Workflow Advisor and how to run various tasks.

Run HDL Workflow with a Script (HDL Coder)

Export, import, or configure an HDL Workflow CLI command script.

Featured Examples

Getting Started with Targeting Intel SoC Devices

Getting Started with Targeting Intel SoC Devices

Please click following link to view the HDL Coder™ example Getting Started with Targeting Intel SoC Devices.

Open Script
Getting Started with the HDL Workflow Command-Line Interface

Getting Started with the HDL Workflow Command-Line Interface

Use the HDL Workflow Advisor to run HDL workflows from the command-line and the 'Export to script' functionality.

Open Script
HDL Coder Support Package for Intel SoC Devices Documentation
Support
Deploying 5G NR Wireless Communications on FPGAs: A Complete MATLAB and Simulink Workflow

Deploying 5G NR Wireless Communications on FPGAs: A Complete MATLAB and Simulink Workflow

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