Use this support package with Intel® Quartus® Prime 18.1
For tool setup instructions, see
See also HDL Language Support and Supported Third-Party Tools and Hardware (HDL Coder).
HDL Coder™ can generate code from your algorithm in Simulink® or MATLAB® and deploy it to standalone FPGA boards. Use:
IP Core Generation to generate an HDL IP core for
your algorithm in MATLAB or Simulink, and then integrate the IP core into the default system
reference design or your own custom reference design that you register
for the board.
FPGA Turnkey to generate HDL code for your
algorithm in Simulink or MATLAB, and the FPGA top level wrapper HDL code for running your
design on a standalone FPGA board. For FPGA development boards that have
more than one FPGA device, only one such device can be used with FPGA
To use these workflows, you must have a supported FPGA board connected to your MATLAB host computer using a supported connection type, and a supported synthesis tool.
|Device Family||Board||IP Core Generation||FPGA Turnkey|
Altera® Arria® II
|Arria II GX FPGA Development Kit||X|
Altera Cyclone® III
|Cyclone III FPGA Development Kit||X|
Altera Cyclone IV
|Cyclone IV GX FPGA Development Kit||X|
|DE2-115 Development and Education Board||X|
Altera MAX® 10
Arrow® MAX 10 DECA
Altera Arria 10
Arria 10 GX FPGA development kit
When you use the
IP Core Generation workflow, you can add
support for custom boards. For more information, see Board and Reference Design Registration System (HDL Coder).